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| author | Arthur Heymans <arthur@aheymans.xyz> | 2018-04-10 15:18:38 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-01-23 14:49:57 +0000 |
| commit | 84fdda381224f0371e27ef3f0ad77ee1103cb05a (patch) | |
| tree | 08aa40dd49e214fe0fd05b7960ba3b3c00e55ccb /src/southbridge/intel/i82801gx | |
| parent | c82950bf79285fa838b6fbaf019a5638316ba053 (diff) | |
| download | coreboot-84fdda381224f0371e27ef3f0ad77ee1103cb05a.tar.gz coreboot-84fdda381224f0371e27ef3f0ad77ee1103cb05a.tar.bz2 coreboot-84fdda381224f0371e27ef3f0ad77ee1103cb05a.zip | |
nb/intel/pineview: Use parallel MP init
Remove guards around CPU code on which all platforms use parallel MP
init code.
This removes the option to disable HT siblings.
Tested on Foxconn D41S.
Change-Id: I89f7d514d75fe933c3a8858da37004419189674b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/25602
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/i82801gx')
| -rw-r--r-- | src/southbridge/intel/i82801gx/lpc.c | 5 |
1 files changed, 0 insertions, 5 deletions
diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 5ad05c73ad2c..7497c7968cea 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -350,11 +350,6 @@ static void i82801gx_lock_smm(struct device *dev) printk(BIOS_DEBUG, "S3 wakeup, enabling ACPI via APMC\n"); outb(APM_CNT_ACPI_ENABLE, APM_CNT); } - /* Don't allow evil boot loaders, kernels, or - * userspace applications to deceive us: - */ - if (!IS_ENABLED(CONFIG_PARALLEL_MP)) - smm_lock(); #if TEST_SMM_FLASH_LOCKDOWN /* Now try this: */ |