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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2020-08-19 21:40:21 +0200 |
|---|---|---|
| committer | Michael Niewöhner <foss@mniewoehner.de> | 2020-09-21 16:29:35 +0000 |
| commit | 131d9f5190a1e5b6fd5a47fecbe5f7eef002c0ef (patch) | |
| tree | accfc86126dba3bf22fe731689ee791894a3bcaa /src/southbridge/intel/i82801ix/dmi_setup.c | |
| parent | b69bbfe1ef52421f0bbe1e632d99dc264660ee02 (diff) | |
| download | coreboot-131d9f5190a1e5b6fd5a47fecbe5f7eef002c0ef.tar.gz coreboot-131d9f5190a1e5b6fd5a47fecbe5f7eef002c0ef.tar.bz2 coreboot-131d9f5190a1e5b6fd5a47fecbe5f7eef002c0ef.zip | |
src/southbridge: Drop unneeded empty lines
Change-Id: I02aa1e2a9a9061b34b91f832d96123a8595d61b7
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44592
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Diffstat (limited to 'src/southbridge/intel/i82801ix/dmi_setup.c')
| -rw-r--r-- | src/southbridge/intel/i82801ix/dmi_setup.c | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/southbridge/intel/i82801ix/dmi_setup.c b/src/southbridge/intel/i82801ix/dmi_setup.c index ffc57f2e1a36..cbb52c4a6c97 100644 --- a/src/southbridge/intel/i82801ix/dmi_setup.c +++ b/src/southbridge/intel/i82801ix/dmi_setup.c @@ -38,7 +38,6 @@ void i82801ix_dmi_setup(void) RCBA8(RCBA_BCR) = 0x45; RCBA32(RCBA_CIR6) &= ~(1 << 7); - /* VC1 setup for isochronous transfers: */ /* Set VC1 virtual channel id to 1. */ @@ -60,7 +59,6 @@ void i82801ix_dmi_setup(void) /* Enable VC1. */ RCBA32(RCBA_V1CTL) |= (1 << 31); - /* Setup RCRB: */ /* Set component id to 2 for southbridge, northbridge has id 1. */ |