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| author | Felix Held <felix-coreboot@felixheld.de> | 2024-02-06 16:55:29 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-02-23 15:13:37 +0000 |
| commit | 0d19289e840f9c711f50a74437d1b3856222db03 (patch) | |
| tree | ca4e8ce2d51dfa9d10deceb28393a28c061a0952 /src/southbridge/intel/i82801ix/lpc.c | |
| parent | a138cfb422109018ba35c8f5d82621717eaf0611 (diff) | |
| download | coreboot-0d19289e840f9c711f50a74437d1b3856222db03.tar.gz coreboot-0d19289e840f9c711f50a74437d1b3856222db03.tar.bz2 coreboot-0d19289e840f9c711f50a74437d1b3856222db03.zip | |
arch/x86/ioapic: use uintptr_t for IOAPIC base address
Use uintptr_t for the IOAPIC base parameter of the various IOAPIC-
related functions to avoid needing type casts in the callers. This also
allows dropping the VIO_APIC_VADDR define and consistently use the
IO_APIC_ADDR define instead.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I912943e923ff092708e90138caa5e1daf269a69f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80358
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Diffstat (limited to 'src/southbridge/intel/i82801ix/lpc.c')
| -rw-r--r-- | src/southbridge/intel/i82801ix/lpc.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index 91b7456d54c2..0adc1b90c02a 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -34,9 +34,9 @@ static void i82801ix_enable_apic(struct device *dev) RCBA8(0x31ff); /* Lock maximum redirection entries (MRE), R/WO register. */ - ioapic_lock_max_vectors(VIO_APIC_VADDR); + ioapic_lock_max_vectors(IO_APIC_ADDR); - register_new_ioapic_gsi0(VIO_APIC_VADDR); + register_new_ioapic_gsi0(IO_APIC_ADDR); } static void i82801ix_enable_serial_irqs(struct device *dev) |