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| author | Arthur Heymans <arthur@aheymans.xyz> | 2017-04-09 20:48:37 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-07-21 15:44:19 +0000 |
| commit | 349e08535a7666cabe52ebc331e3bce5468b786b (patch) | |
| tree | 6e337227e7450ac1d931ac61eaf939ae936ad50c /src/southbridge/intel/i82801jx/Makefile.inc | |
| parent | 7b9c139ac26eded525980e896b354c99c08cdca7 (diff) | |
| download | coreboot-349e08535a7666cabe52ebc331e3bce5468b786b.tar.gz coreboot-349e08535a7666cabe52ebc331e3bce5468b786b.tar.bz2 coreboot-349e08535a7666cabe52ebc331e3bce5468b786b.zip | |
sb/intel/i82801jx: Add correct PCI ids and change names
Change-Id: Ic9226098dafa2465aa5fccc72c442de2b94e44c7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19249
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/southbridge/intel/i82801jx/Makefile.inc')
| -rw-r--r-- | src/southbridge/intel/i82801jx/Makefile.inc | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/src/southbridge/intel/i82801jx/Makefile.inc b/src/southbridge/intel/i82801jx/Makefile.inc index 975a068e6983..9121c3d96416 100644 --- a/src/southbridge/intel/i82801jx/Makefile.inc +++ b/src/southbridge/intel/i82801jx/Makefile.inc @@ -16,7 +16,7 @@ ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82801JX),y) -ramstage-y += i82801ix.c +ramstage-y += i82801jx.c ramstage-y += pci.c ramstage-y += lpc.c ramstage-y += pcie.c @@ -36,8 +36,6 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/smm/smmrelocate.S smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c -romstage-y += early_init.c romstage-y += early_smbus.c -romstage-y += dmi_setup.c endif |