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| author | Angel Pons <th3fanbus@gmail.com> | 2020-06-08 02:09:33 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-06-12 00:12:17 +0000 |
| commit | 2048cb43863f014fedc4ff44233d49410f0cee5e (patch) | |
| tree | 1be140c2bf5bd48f278039d1c32d5fa382379a86 /src/southbridge/intel/i82801jx/early_init.c | |
| parent | efd23d92efb982f74b8473201bc93b1c0ad64bc8 (diff) | |
| download | coreboot-2048cb43863f014fedc4ff44233d49410f0cee5e.tar.gz coreboot-2048cb43863f014fedc4ff44233d49410f0cee5e.tar.bz2 coreboot-2048cb43863f014fedc4ff44233d49410f0cee5e.zip | |
sb/intel/i82801jx: Use PCI bitwise ops
Tested with BUILD_TIMELESS=1, Intel DG43GT does not change.
Change-Id: Ifd5b8cd7644811a56afae82468c8eb0a7b6b7ff9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42157
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/i82801jx/early_init.c')
| -rw-r--r-- | src/southbridge/intel/i82801jx/early_init.c | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/src/southbridge/intel/i82801jx/early_init.c b/src/southbridge/intel/i82801jx/early_init.c index 8504c09bd080..8ed7a41784d7 100644 --- a/src/southbridge/intel/i82801jx/early_init.c +++ b/src/southbridge/intel/i82801jx/early_init.c @@ -59,9 +59,8 @@ void i82801jx_setup_bars(void) /* Set up GPIOBASE. */ pci_write_config32(d31f0, D31F0_GPIO_BASE, DEFAULT_GPIOBASE); - /* Enable GPIO. */ - pci_write_config8(d31f0, D31F0_GPIO_CNTL, - pci_read_config8(d31f0, D31F0_GPIO_CNTL) | 0x10); + /* Enable GPIO. */ + pci_or_config8(d31f0, D31F0_GPIO_CNTL, 0x10); } #define TCO_BASE 0x60 @@ -96,6 +95,8 @@ void i82801jx_early_init(void) and 0xe (required if ME is disabled but present), bit 31 locks it. The other bits are 'must write'. */ u8 reg8 = pci_read_config8(d31f0, 0xac); + + /* FIXME: It's a 8-bit variable!!! */ reg8 |= (1 << 31) | (1 << 30) | (1 << 20) | (3 << 8); pci_write_config8(d31f0, 0xac, reg8); |