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| author | Arthur Heymans <arthur@aheymans.xyz> | 2017-12-24 08:11:13 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-06-29 07:45:30 +0000 |
| commit | a8a9f34e9b7be8781c06c9d6fcc39f52bf31bd23 (patch) | |
| tree | b674190e4efe1c2a814a2638b3a20d92701c353d /src/southbridge/intel/i82801jx | |
| parent | e798e6a0b946fe5a3964bc38fb7783a219adf177 (diff) | |
| download | coreboot-a8a9f34e9b7be8781c06c9d6fcc39f52bf31bd23.tar.gz coreboot-a8a9f34e9b7be8781c06c9d6fcc39f52bf31bd23.tar.bz2 coreboot-a8a9f34e9b7be8781c06c9d6fcc39f52bf31bd23.zip | |
sb/intel/i82801{g,j}x: Automatically generate ACPI PIRQ tables
Both southbridges need to be done at once since this southbridge code
is used for different northbridges, which fails to compile when done
separately.
This needs an acpi_name functions in the northbridge code to be
defined.
TESTED on Intel DG43GT: show correct PIRQ ACPI entries in
/sys/firmware/acpi/tables/SSDT.
Change-Id: I286d251ddf8fcae27dd07011a1cd62d8f4847683
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22981
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/southbridge/intel/i82801jx')
| -rw-r--r-- | src/southbridge/intel/i82801jx/Kconfig | 1 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801jx/lpc.c | 8 |
2 files changed, 9 insertions, 0 deletions
diff --git a/src/southbridge/intel/i82801jx/Kconfig b/src/southbridge/intel/i82801jx/Kconfig index e418a94f60c1..2c98f72e4b6b 100644 --- a/src/southbridge/intel/i82801jx/Kconfig +++ b/src/southbridge/intel/i82801jx/Kconfig @@ -19,6 +19,7 @@ config SOUTHBRIDGE_INTEL_I82801JX select SOUTHBRIDGE_INTEL_COMMON select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI + select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ select IOAPIC select HAVE_USBDEBUG select HAVE_HARD_RESET diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index ff86f0fddd01..cd5e3078b012 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -34,6 +34,7 @@ #include "i82801jx.h" #include "nvs.h" #include <southbridge/intel/common/pciehp.h> +#include <southbridge/intel/common/acpi_pirq_gen.h> #include <drivers/intel/gma/i915.h> #define NMI_OFF 0 @@ -720,12 +721,18 @@ static void southbridge_inject_dsdt(struct device *dev) } } +static const char *lpc_acpi_name(const struct device *dev) +{ + return "LPCB"; +} + static void southbridge_fill_ssdt(struct device *device) { struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); config_t *chip = dev->chip_info; intel_acpi_pcie_hotplug_generator(chip->pcie_hotplug_map, 8); + intel_acpi_gen_def_acpi_pirq(device); } static struct pci_operations pci_ops = { @@ -739,6 +746,7 @@ static struct device_operations device_ops = { .acpi_inject_dsdt_generator = southbridge_inject_dsdt, .write_acpi_tables = acpi_write_hpet, .acpi_fill_ssdt_generator = southbridge_fill_ssdt, + .acpi_name = lpc_acpi_name, .init = lpc_init, .scan_bus = scan_lpc_bus, .ops_pci = &pci_ops, |