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| author | Patrick Rudolph <siro@das-labor.org> | 2018-10-01 19:17:11 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-10-22 08:35:25 +0000 |
| commit | 45022ae056cdbf58429b77daf2da176306312801 (patch) | |
| tree | 4218666e3c14e41232778c4ceff301292b3c61d9 /src/southbridge/intel/ibexpeak | |
| parent | 33fcaf91ff825ad0adf0a2a483e6a296ed4e0e31 (diff) | |
| download | coreboot-45022ae056cdbf58429b77daf2da176306312801.tar.gz coreboot-45022ae056cdbf58429b77daf2da176306312801.tar.bz2 coreboot-45022ae056cdbf58429b77daf2da176306312801.zip | |
intel: Use CF9 reset (part 1)
Add SOUTHBRIDGE_INTEL_COMMON_RESET for all Intel platforms that used to
perform a "system reset" in their hard_reset() implementation. Replace
all duplicate CF9 reset implementations for these platforms.
Change-Id: I8e359b0c4d5a1060edd0940d24c2f78dfed8a590
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/28862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/southbridge/intel/ibexpeak')
| -rw-r--r-- | src/southbridge/intel/ibexpeak/Kconfig | 1 | ||||
| -rw-r--r-- | src/southbridge/intel/ibexpeak/Makefile.inc | 2 |
2 files changed, 0 insertions, 3 deletions
diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig index 5b085b7e1dd5..fe6526dc886b 100644 --- a/src/southbridge/intel/ibexpeak/Kconfig +++ b/src/southbridge/intel/ibexpeak/Kconfig @@ -22,7 +22,6 @@ config SOUTH_BRIDGE_OPTIONS # dummy def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES select IOAPIC - select HAVE_HARD_RESET select HAVE_USBDEBUG select HAVE_SMI_HANDLER select USE_WATCHDOG_ON_BOOT diff --git a/src/southbridge/intel/ibexpeak/Makefile.inc b/src/southbridge/intel/ibexpeak/Makefile.inc index 7714f9578af4..906652d56521 100644 --- a/src/southbridge/intel/ibexpeak/Makefile.inc +++ b/src/southbridge/intel/ibexpeak/Makefile.inc @@ -31,7 +31,6 @@ ramstage-y += ../common/pciehp.c ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c ramstage-y += ../bd82x6x/me_status.c -ramstage-y += ../bd82x6x/reset.c ramstage-y += ../bd82x6x/watchdog.c ramstage-$(CONFIG_ELOG) += ../bd82x6x/elog.c @@ -41,7 +40,6 @@ ramstage-y += smi.c smm-y += smihandler.c me.c ../bd82x6x/me_8.x.c ../bd82x6x/finalize.c ../bd82x6x/pch.c romstage-y += ../bd82x6x/early_usb.c early_smbus.c ../bd82x6x/early_me.c ../bd82x6x/me_status.c ../common/gpio.c early_thermal.c -romstage-y += ../bd82x6x/reset.c romstage-y += ../bd82x6x/early_rcba.c romstage-$(CONFIG_SOUTHBRIDGE_INTEL_BD82X6X) += ../bd82x6x/early_spi.c romstage-$(CONFIG_SOUTHBRIDGE_INTEL_C216) += ../bd82x6x/early_spi.c |