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| author | Angel Pons <th3fanbus@gmail.com> | 2020-11-04 00:38:28 +0100 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-11-07 14:18:35 +0000 |
| commit | f47117134d0b19914eb266af2f4f8094ca7621e6 (patch) | |
| tree | 00a08d32f37c6b2a7bd58d375268396646c46a0c /src/southbridge/intel/lynxpoint/early_pch.c | |
| parent | 4b519f7c62d55b06c1d99ee6b39a0226475777ad (diff) | |
| download | coreboot-f47117134d0b19914eb266af2f4f8094ca7621e6.tar.gz coreboot-f47117134d0b19914eb266af2f4f8094ca7621e6.tar.bz2 coreboot-f47117134d0b19914eb266af2f4f8094ca7621e6.zip | |
sb/intel: Don't set ACPI_EN twice
It is already done once when enabling PMBASE in early init.
Change-Id: I14289c9164ee1488c192fce721d86c89fa5cc736
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47207
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/southbridge/intel/lynxpoint/early_pch.c')
| -rw-r--r-- | src/southbridge/intel/lynxpoint/early_pch.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index 465aa1e710d2..8cc6a8760ca0 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -40,7 +40,7 @@ static void pch_enable_bars(void) pci_write_config32(PCH_LPC_DEV, PMBASE, DEFAULT_PMBASE | 1); /* Enable ACPI BAR */ - pci_write_config8(PCH_LPC_DEV, ACPI_CNTL, 0x80); + pci_write_config8(PCH_LPC_DEV, ACPI_CNTL, ACPI_EN); pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1); |