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| author | Angel Pons <th3fanbus@gmail.com> | 2020-09-24 18:03:18 +0200 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2020-10-14 08:37:36 +0000 |
| commit | 2aaf7c0a1d1a895805772fe5f878606161c8d3c5 (patch) | |
| tree | 5d590e1379ec8098b6a8040a5357075d309f86c9 /src/southbridge/intel/lynxpoint/lpc.c | |
| parent | 2ead36334050ac692e64adc59a97320d8792adcc (diff) | |
| download | coreboot-2aaf7c0a1d1a895805772fe5f878606161c8d3c5.tar.gz coreboot-2aaf7c0a1d1a895805772fe5f878606161c8d3c5.tar.bz2 coreboot-2aaf7c0a1d1a895805772fe5f878606161c8d3c5.zip | |
haswell/lynxpoint: Align cosmetics with Broadwell
Tested with BUILD_TIMELESS=1, Google Wolf does not change.
Change-Id: Ibd8430352e860ffc0e2030fd7bc73582982f4695
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45698
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/lynxpoint/lpc.c')
| -rw-r--r-- | src/southbridge/intel/lynxpoint/lpc.c | 11 |
1 files changed, 5 insertions, 6 deletions
diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index e5614303ccce..fad83b1612a1 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -115,7 +115,7 @@ static void pch_pirq_init(struct device *dev) */ for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { - u8 int_pin=0, int_line=0; + u8 int_pin = 0, int_line = 0; if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) continue; @@ -446,7 +446,7 @@ static void enable_lp_clock_gating(struct device *dev) reg32 &= ~(1 << 29); // LPC Dynamic else reg32 |= (1 << 29); // LPC Dynamic - reg32 |= (1UL << 31); // LP LPC + reg32 |= (1 << 31); // LP LPC reg32 |= (1 << 30); // LP BLA reg32 |= (1 << 28); // GPIO Dynamic reg32 |= (1 << 27); // HPET Dynamic @@ -565,7 +565,7 @@ static void pch_lpc_add_mmio_resources(struct device *dev) res->base = (resource_t)(uintptr_t)DEFAULT_RCBA; res->size = 16 * 1024; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | - IORESOURCE_FIXED | IORESOURCE_RESERVE; + IORESOURCE_FIXED | IORESOURCE_RESERVE; } /* Check LPC Memory Decode register. */ @@ -577,7 +577,7 @@ static void pch_lpc_add_mmio_resources(struct device *dev) res->base = reg; res->size = 16 * 1024; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | - IORESOURCE_FIXED | IORESOURCE_RESERVE; + IORESOURCE_FIXED | IORESOURCE_RESERVE; } } } @@ -645,8 +645,7 @@ static void pch_lpc_add_io_resources(struct device *dev) res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; /* GPIOBASE */ - pch_lpc_add_io_resource(dev, get_gpiobase(), DEFAULT_GPIOSIZE, - GPIO_BASE); + pch_lpc_add_io_resource(dev, get_gpiobase(), DEFAULT_GPIOSIZE, GPIO_BASE); /* PMBASE */ pch_lpc_add_io_resource(dev, get_pmbase(), 256, PMBASE); |