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| author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-02-26 10:30:52 -0700 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2021-04-27 11:06:38 +0000 |
| commit | f62c49474fd6739558e308df0603350dd73b516e (patch) | |
| tree | 64ccdfddfcc57c0f6d01d9eb58d99f732b5b302e /src/southbridge/intel/lynxpoint/lpc.c | |
| parent | d26cdb3ea3019d76dd39cfcd8c46bd36e8860054 (diff) | |
| download | coreboot-f62c49474fd6739558e308df0603350dd73b516e.tar.gz coreboot-f62c49474fd6739558e308df0603350dd73b516e.tar.bz2 coreboot-f62c49474fd6739558e308df0603350dd73b516e.zip | |
sb/intel/common: Refactor _PRT generation to support GSI-based tables
Newer Intel SoCs also support _PRT tables, but they route PCI devices to
more than just PIRQs, and statically specify IRQs instead of using link
devices. Extend/refactor intel_acpi_gen_def_acpi_pirq to support this
additional use case.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ica420a3d12fd1d64c8fe6e4b326fd779b3f10868
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50857
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/southbridge/intel/lynxpoint/lpc.c')
| -rw-r--r-- | src/southbridge/intel/lynxpoint/lpc.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 71e4d7460270..8d9b4510d375 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -17,6 +17,7 @@ #include "pch.h" #include <acpi/acpigen.h> #include <southbridge/intel/common/acpi_pirq_gen.h> +#include <southbridge/intel/common/rcba_pirq.h> #include <southbridge/intel/common/rtc.h> #include <southbridge/intel/common/spi.h> #include <types.h> |