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author | Martin Roth <martin@coreboot.org> | 2021-10-01 14:53:22 -0600 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2021-10-05 18:07:08 +0000 |
commit | 26f97f9532933da3c1d72a7918c8a24457bbc1c0 (patch) | |
tree | 8c25279e58ef541fae197ec193f5642a9b21b2d4 /src/southbridge/intel | |
parent | 50863daef8ed75c0cb3dfd375e7622c898de5821 (diff) | |
download | coreboot-26f97f9532933da3c1d72a7918c8a24457bbc1c0.tar.gz coreboot-26f97f9532933da3c1d72a7918c8a24457bbc1c0.tar.bz2 coreboot-26f97f9532933da3c1d72a7918c8a24457bbc1c0.zip |
src/soc to src/superio: Fix spelling errors
These issues were found and fixed by codespell, a useful tool for
finding spelling errors.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ieafbc93e49fcef198ac6e31fc8a3b708c395e08e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58082
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel')
-rw-r--r-- | src/southbridge/intel/bd82x6x/azalia.c | 2 | ||||
-rw-r--r-- | src/southbridge/intel/bd82x6x/lpc.c | 2 | ||||
-rw-r--r-- | src/southbridge/intel/i82371eb/acpi_tables.c | 2 | ||||
-rw-r--r-- | src/southbridge/intel/i82371eb/smbus.c | 2 | ||||
-rw-r--r-- | src/southbridge/intel/i82801dx/lpc.c | 2 | ||||
-rw-r--r-- | src/southbridge/intel/i82801gx/azalia.c | 2 | ||||
-rw-r--r-- | src/southbridge/intel/i82801ix/azalia.c | 2 | ||||
-rw-r--r-- | src/southbridge/intel/i82801jx/azalia.c | 2 | ||||
-rw-r--r-- | src/southbridge/intel/ibexpeak/azalia.c | 2 | ||||
-rw-r--r-- | src/southbridge/intel/ibexpeak/lpc.c | 2 | ||||
-rw-r--r-- | src/southbridge/intel/lynxpoint/lpc.c | 2 | ||||
-rw-r--r-- | src/southbridge/intel/lynxpoint/me_status.c | 2 | ||||
-rw-r--r-- | src/southbridge/intel/lynxpoint/pch.h | 2 |
13 files changed, 13 insertions, 13 deletions
diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c index 1f14c422a81c..3b07a1529816 100644 --- a/src/southbridge/intel/bd82x6x/azalia.c +++ b/src/southbridge/intel/bd82x6x/azalia.c @@ -162,7 +162,7 @@ static void azalia_init(struct device *dev) if (!res) return; - // NOTE this will break as soon as the Azalia get's a bar above 4G. + // NOTE this will break as soon as the Azalia gets a bar above 4G. // Is there anything we can do about it? base = res2mmio(res, 0, 0); printk(BIOS_DEBUG, "Azalia: base = %p\n", base); diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index b4f0c4c5fc8e..dfebaf0dace1 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -31,7 +31,7 @@ typedef struct southbridge_intel_bd82x6x_config config_t; /** - * Set miscellanous static southbridge features. + * Set miscellaneous static southbridge features. * * @param dev PCI device with I/O APIC control registers */ diff --git a/src/southbridge/intel/i82371eb/acpi_tables.c b/src/southbridge/intel/i82371eb/acpi_tables.c index 7507cd5d5da1..41fc4eeaa106 100644 --- a/src/southbridge/intel/i82371eb/acpi_tables.c +++ b/src/southbridge/intel/i82371eb/acpi_tables.c @@ -29,7 +29,7 @@ void generate_cpu_entries(const struct device *device) int numcpus = determine_total_number_of_cores(); printk(BIOS_DEBUG, "Found %d CPU(s).\n", numcpus); - /* without the outer scope, furhter ssdt addition will end up + /* without the outer scope, further ssdt addition will end up * within the processor statement */ acpigen_write_scope("\\_SB"); for (cpu=0; cpu < numcpus; cpu++) { diff --git a/src/southbridge/intel/i82371eb/smbus.c b/src/southbridge/intel/i82371eb/smbus.c index 988d7418d3cb..5b9f8be30e9c 100644 --- a/src/southbridge/intel/i82371eb/smbus.c +++ b/src/southbridge/intel/i82371eb/smbus.c @@ -27,7 +27,7 @@ static void pwrmgt_enable(struct device *dev) * bit25 (lid_pol): 1=invert lid polarity * bit24 (sm_freeze): 1=freeze idle and standby timers * bit16 (end of smi): 0=disable smi assertion (cleared by hw) - * bits8-15,26: global standby timer inital count 127 * 4minutes + * bits8-15,26: global standby timer initial count 127 * 4minutes * bit2 (thrm_pol): 1=active low THRM# * bit0 (smi_en): 1=disable smi generation upon smi event */ diff --git a/src/southbridge/intel/i82801dx/lpc.c b/src/southbridge/intel/i82801dx/lpc.c index 6ff606422b12..321c60536628 100644 --- a/src/southbridge/intel/i82801dx/lpc.c +++ b/src/southbridge/intel/i82801dx/lpc.c @@ -32,7 +32,7 @@ static void i82801dx_enable_acpi(struct device *dev) } /** - * Set miscellanous static southbridge features. + * Set miscellaneous static southbridge features. * * @param dev PCI device with I/O APIC control registers */ diff --git a/src/southbridge/intel/i82801gx/azalia.c b/src/southbridge/intel/i82801gx/azalia.c index fde06b4aacc4..0473de64de9c 100644 --- a/src/southbridge/intel/i82801gx/azalia.c +++ b/src/southbridge/intel/i82801gx/azalia.c @@ -190,7 +190,7 @@ static void azalia_init(struct device *dev) if (!res) return; - // NOTE this will break as soon as the Azalia get's a bar above 4G. + // NOTE this will break as soon as the Azalia gets a bar above 4G. // Is there anything we can do about it? base = res2mmio(res, 0, 0); printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)(uintptr_t)base); diff --git a/src/southbridge/intel/i82801ix/azalia.c b/src/southbridge/intel/i82801ix/azalia.c index ff890a265f14..90d784cd652f 100644 --- a/src/southbridge/intel/i82801ix/azalia.c +++ b/src/southbridge/intel/i82801ix/azalia.c @@ -183,7 +183,7 @@ static void azalia_init(struct device *dev) if (!res) return; - // NOTE this will break as soon as the Azalia get's a bar above 4G. + // NOTE this will break as soon as the Azalia gets a bar above 4G. // Is there anything we can do about it? base = res2mmio(res, 0, 0); printk(BIOS_DEBUG, "Azalia: base = %p\n", base); diff --git a/src/southbridge/intel/i82801jx/azalia.c b/src/southbridge/intel/i82801jx/azalia.c index 5efbc9f60121..885c332f8f55 100644 --- a/src/southbridge/intel/i82801jx/azalia.c +++ b/src/southbridge/intel/i82801jx/azalia.c @@ -183,7 +183,7 @@ static void azalia_init(struct device *dev) if (!res) return; - // NOTE this will break as soon as the Azalia get's a bar above 4G. + // NOTE this will break as soon as the Azalia gets a bar above 4G. // Is there anything we can do about it? base = res2mmio(res, 0, 0); printk(BIOS_DEBUG, "Azalia: base = %p\n", base); diff --git a/src/southbridge/intel/ibexpeak/azalia.c b/src/southbridge/intel/ibexpeak/azalia.c index ef781b71740f..683715fd6bd9 100644 --- a/src/southbridge/intel/ibexpeak/azalia.c +++ b/src/southbridge/intel/ibexpeak/azalia.c @@ -162,7 +162,7 @@ static void azalia_init(struct device *dev) if (!res) return; - // NOTE this will break as soon as the Azalia get's a bar above 4G. + // NOTE this will break as soon as the Azalia gets a bar above 4G. // Is there anything we can do about it? base = res2mmio(res, 0, 0); printk(BIOS_DEBUG, "Azalia: base = %p\n", base); diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 8cc9b42c1776..c14c6a28b1e4 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -28,7 +28,7 @@ typedef struct southbridge_intel_ibexpeak_config config_t; /** - * Set miscellanous static southbridge features. + * Set miscellaneous static southbridge features. * * @param dev PCI device with I/O APIC control registers */ diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index f3c08d885f08..d0eb4b33f010 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -25,7 +25,7 @@ #define NMI_OFF 0 /** - * Set miscellanous static southbridge features. + * Set miscellaneous static southbridge features. * * @param dev PCI device with I/O APIC control registers */ diff --git a/src/southbridge/intel/lynxpoint/me_status.c b/src/southbridge/intel/lynxpoint/me_status.c index 82a8f8ed0ab3..fb4490f86707 100644 --- a/src/southbridge/intel/lynxpoint/me_status.c +++ b/src/southbridge/intel/lynxpoint/me_status.c @@ -187,7 +187,7 @@ void intel_me_status(struct me_hfs *hfs, struct me_hfs2 *hfs2) break; default: - printk(BIOS_DEBUG, "Unknown phase: 0x%02x sate: 0x%02x", + printk(BIOS_DEBUG, "Unknown phase: 0x%02x state: 0x%02x", hfs2->progress_code, hfs2->current_state); } printk(BIOS_DEBUG, "\n"); diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 598c2dc7b216..7d9fc6d6afd2 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -647,7 +647,7 @@ void mainboard_config_rcba(void); #define SPIBAR16(x) RCBA16((x) + SPIBAR_OFFSET) #define SPIBAR32(x) RCBA32((x) + SPIBAR_OFFSET) -/* Reigsters within the SPIBAR */ +/* Registers within the SPIBAR */ #define SSFC 0x91 #define FDOC 0xb0 #define FDOD 0xb4 |