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| author | Aamir Bohra <aamir.bohra@intel.com> | 2018-07-01 00:31:05 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2018-11-23 06:16:15 +0000 |
| commit | 4041bcf629c9b0239cca7a71091f6e6f0c669b4b (patch) | |
| tree | 74d66674c3f1b5207a930b9a90ca96fe944d3b88 /src/southbridge/nvidia | |
| parent | 2fd2923aebae63bdf4567f70d933831f44e082ed (diff) | |
| download | coreboot-4041bcf629c9b0239cca7a71091f6e6f0c669b4b.tar.gz coreboot-4041bcf629c9b0239cca7a71091f6e6f0c669b4b.tar.bz2 coreboot-4041bcf629c9b0239cca7a71091f6e6f0c669b4b.zip | |
mb/intel/icelake_rvp: Add ICL U and Y RVP DIMM configuration
List of ICL board variants
1. ICL-U
DDR4 - All possible DDR4 memory type
LPDDR4 - Memory down fixed DIMM configuration
2. ICL-Y
All LPDDR4 DIMM on platform
This patch ensures to have all proper SPD configuration.
Change-Id: Id596a3c85b13559b3002dcadfee9c945256e28e7
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/29770
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Diffstat (limited to 'src/southbridge/nvidia')
0 files changed, 0 insertions, 0 deletions