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| author | Eric Biederman <ebiederm@xmission.com> | 2004-11-04 11:04:33 +0000 |
|---|---|---|
| committer | Eric Biederman <ebiederm@xmission.com> | 2004-11-04 11:04:33 +0000 |
| commit | 018d8dd60f2cc0c82faac0ee2657daa163dd43e7 (patch) | |
| tree | 528de120d262a9df05ce8b6119f593c85fa6b809 /src/southbridge/ricoh/rl5c476/rl5c476.c | |
| parent | 4403f6082372d069e3cabe0918d9af5f9c1dccf6 (diff) | |
| download | coreboot-018d8dd60f2cc0c82faac0ee2657daa163dd43e7.tar.gz coreboot-018d8dd60f2cc0c82faac0ee2657daa163dd43e7.tar.bz2 coreboot-018d8dd60f2cc0c82faac0ee2657daa163dd43e7.zip | |
- Update abuild.sh so it will rebuild successfull builds
- Move pci_set_method out of hardwaremain.c
- Re-add debugging name field but only include the CONFIG_CHIP_NAME is
enabled. All instances are now wrapped in CHIP_NAME
- Many minor cleanups so most ports build.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1737 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/ricoh/rl5c476/rl5c476.c')
| -rw-r--r-- | src/southbridge/ricoh/rl5c476/rl5c476.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/southbridge/ricoh/rl5c476/rl5c476.c b/src/southbridge/ricoh/rl5c476/rl5c476.c index 4240f96a400f..2f42fe752c6b 100644 --- a/src/southbridge/ricoh/rl5c476/rl5c476.c +++ b/src/southbridge/ricoh/rl5c476/rl5c476.c @@ -223,6 +223,6 @@ static struct pci_driver ricoh_rl5c476_driver __pci_driver = { }; struct chip_operations southbridge_ricoh_rl5c476_control = { + CHIP_NAME("RICOH RL5C476") .enable = southbridge_init, - .name = "RICOH RL5C476" }; |