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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2020-08-19 21:40:21 +0200 |
|---|---|---|
| committer | Michael Niewöhner <foss@mniewoehner.de> | 2020-09-21 16:29:35 +0000 |
| commit | 131d9f5190a1e5b6fd5a47fecbe5f7eef002c0ef (patch) | |
| tree | accfc86126dba3bf22fe731689ee791894a3bcaa /src/southbridge/ricoh/rl5c476/rl5c476.c | |
| parent | b69bbfe1ef52421f0bbe1e632d99dc264660ee02 (diff) | |
| download | coreboot-131d9f5190a1e5b6fd5a47fecbe5f7eef002c0ef.tar.gz coreboot-131d9f5190a1e5b6fd5a47fecbe5f7eef002c0ef.tar.bz2 coreboot-131d9f5190a1e5b6fd5a47fecbe5f7eef002c0ef.zip | |
src/southbridge: Drop unneeded empty lines
Change-Id: I02aa1e2a9a9061b34b91f832d96123a8595d61b7
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44592
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Diffstat (limited to 'src/southbridge/ricoh/rl5c476/rl5c476.c')
| -rw-r--r-- | src/southbridge/ricoh/rl5c476/rl5c476.c | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/src/southbridge/ricoh/rl5c476/rl5c476.c b/src/southbridge/ricoh/rl5c476/rl5c476.c index 73cb2e1fdadf..e0744b314e87 100644 --- a/src/southbridge/ricoh/rl5c476/rl5c476.c +++ b/src/southbridge/ricoh/rl5c476/rl5c476.c @@ -107,11 +107,9 @@ static void rl5c476_init(struct device *dev) pc16->moffl0 = 0; pc16->moffh0 = 0x40; - /* set I/O width for Auto Data width */ pc16->ioctrl = 0x22; - /* enable I/O window 0 and 1 */ pc16->awinen = 0xc1; @@ -125,7 +123,6 @@ static void rl5c476_init(struct device *dev) pc16->igctrl = 0x69; - /* 16 bit CF always have first config byte at 0x200 into * Config structure, but CF+ may not according to spec - * should locate through reading tuple data, but this should |