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| author | Angel Pons <th3fanbus@gmail.com> | 2020-07-07 22:13:49 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-07-09 23:45:38 +0000 |
| commit | 2047588de5d0fc12cbc7515f7efa8a9ebe8b0be0 (patch) | |
| tree | 7c10765404845e8647d34461ac9fc7cf5c0f8e0a /src/southbridge/ti | |
| parent | f29e0ea2a05a8259753639d6c5b54e8415cf2a2a (diff) | |
| download | coreboot-2047588de5d0fc12cbc7515f7efa8a9ebe8b0be0.tar.gz coreboot-2047588de5d0fc12cbc7515f7efa8a9ebe8b0be0.tar.bz2 coreboot-2047588de5d0fc12cbc7515f7efa8a9ebe8b0be0.zip | |
sb/ti/pci7420: Drop dead code
This code is not even being build-tested. Drop it before it grows moss.
Change-Id: I51a2b71abc7762b550f69f2980dd34f0e4947ab5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43219
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/ti')
| -rw-r--r-- | src/southbridge/ti/pci7420/cardbus.c | 18 | ||||
| -rw-r--r-- | src/southbridge/ti/pci7420/firewire.c | 9 |
2 files changed, 0 insertions, 27 deletions
diff --git a/src/southbridge/ti/pci7420/cardbus.c b/src/southbridge/ti/pci7420/cardbus.c index 02c4a01c0e4a..6ef08a306743 100644 --- a/src/southbridge/ti/pci7420/cardbus.c +++ b/src/southbridge/ti/pci7420/cardbus.c @@ -8,10 +8,6 @@ #include "pci7420.h" #include "chip.h" -#ifdef ODD_IRQ_FIXUP -static int cardbus_count = 0; -#endif - static void pci7420_cardbus_init(struct device *dev) { u8 reg8; @@ -47,20 +43,6 @@ static void pci7420_cardbus_init(struct device *dev) /* Multifunction routing status */ pci_write_config32(dev, MFUNC, 0x018a1b22); - -#ifdef ODD_IRQ_FIXUP - /* This is a workaround for buggy kernels. This should - * probably be read from the device tree, but as long - * as only one mainboard is using this bridge it does - * not matter. - * - * Basically what we do here is assign INTA to the first - * cardbus controller, and INTB to the second one. We know - * there are only two of them. - */ - pci_write_config8(dev, PCI_INTERRUPT_PIN, cardbus_count); - cardbus_count++; -#endif } static void pci7420_cardbus_read_resources(struct device *dev) diff --git a/src/southbridge/ti/pci7420/firewire.c b/src/southbridge/ti/pci7420/firewire.c index ef06ea6a3b30..a3277451686c 100644 --- a/src/southbridge/ti/pci7420/firewire.c +++ b/src/southbridge/ti/pci7420/firewire.c @@ -11,15 +11,6 @@ static void pci7420_firewire_init(struct device *dev) { printk(BIOS_DEBUG, "TI PCI7420/7620 FireWire init\n"); - -#ifdef ODD_IRQ_FIXUP - /* This is a workaround for buggy kernels. This should - * probably be read from the device tree, but as long - * as only one mainboard is using this bridge it does - * not matter - */ - pci_write_config8(dev, PCI_INTERRUPT_PIN, INTC); -#endif } static struct device_operations ti_pci7420_firewire_ops = { |