first round name simplification. drop the <component>_ prefix.

the prefix was introduced in the early v2 tree many years ago
because our old build system "newconfig" could not handle two files with
the same name in different paths like /path/to/usb.c and
/another/path/to/usb.c correctly. Only one of the files would end up
being compiled into the final image.

Since Kconfig (actually since shortly before we switched to Kconfig) we
don't suffer from that problem anymore. So we could drop the sb700_
prefix from all those filenames (or, the <componentname>_ prefix in general)

- makes it easier to fork off a new chipset
- makes it easier to diff against other chipsets
- storing redundant information in filenames seems wrong

Signed-off-by: <stepan@coresystems.de>

Acked-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6149 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

1 files changed, 151 insertions, 0 deletions

diff --git a/src/southbridge/via/k8t890/host_ctrl.c b/src/southbridge/via/k8t890/host_ctrl.c
new file mode 100644
index 000000000000..43d01ee36926
--- /dev/null
+++ b/src/southbridge/via/k8t890/host_ctrl.c
@@ -0,0 +1,151 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ops.h>
+#include <device/pci_ids.h>
+#include <console/console.h>
+#include <cbmem.h>
+#include <arch/io.h>
+#include "k8t890.h"
+
+/* this may be later merged */
+
+/* This fine tunes the HT link settings, which were loaded by ROM strap. */
+static void host_ctrl_enable_k8t890(struct device *dev)
+{
+	dump_south(dev);
+
+	/*
+	 * Bit 4 is reserved but set by AW. Set PCI to HT outstanding
+	 * requests to 3.
+	 */
+	pci_write_config8(dev, 0xa0, 0x13);
+
+	/*
+	 * NVRAM I/O base at K8T890_NVRAM_IO_BASE
+	 * Some bits are set and reserved.
+	 */
+	pci_write_config8(dev, 0xa2, (K8T890_NVRAM_IO_BASE >> 8));
+
+	/* enable NB NVRAM and enable non-posted PCI writes. */
+	pci_write_config8(dev, 0xa1, 0x8f);
+	/* Arbitration control, some bits are reserved. */
+	pci_write_config8(dev, 0xa5, 0x3c);
+
+	/* Arbitration control 2 */
+	pci_write_config8(dev, 0xa6, 0x80);
+
+	/* this will be possibly removed, when I figure out
+	 * if the ROM SIP is good, second reason is that the
+	 * unknown bits are AGP related, which are dummy on K8T890
+	 */
+
+	writeback(dev, 0xa0, 0x13);	/* Bit4 is reserved! */
+	writeback(dev, 0xa1, 0x8e);	/* Some bits are reserved. */
+	writeback(dev, 0xa2, 0x0e);	/* I/O NVRAM base 0xe00-0xeff disabled. */
+	writeback(dev, 0xa3, 0x31);
+	writeback(dev, 0xa4, 0x30);
+
+	writeback(dev, 0xa5, 0x3c);	/* Some bits reserved. */
+	writeback(dev, 0xa6, 0x80);	/* Some bits reserved. */
+	writeback(dev, 0xa7, 0x86);	/* Some bits reserved. */
+	writeback(dev, 0xa8, 0x7f);	/* Some bits reserved. */
+	writeback(dev, 0xa9, 0xcf);	/* Some bits reserved. */
+	writeback(dev, 0xaa, 0x44);
+	writeback(dev, 0xab, 0x22);
+	writeback(dev, 0xac, 0x35);	/* Maybe bit0 is read-only? */
+
+	writeback(dev, 0xae, 0x22);
+	writeback(dev, 0xaf, 0x40);
+	/* b0 is missing. */
+	writeback(dev, 0xb1, 0x13);
+	writeback(dev, 0xb4, 0x02);	/* Some bits are reserved. */
+	writeback(dev, 0xc0, 0x20);
+	writeback(dev, 0xc1, 0xaa);
+	writeback(dev, 0xc2, 0xaa);
+	writeback(dev, 0xc3, 0x02);
+	writeback(dev, 0xc4, 0x50);
+	writeback(dev, 0xc5, 0x50);
+
+	dump_south(dev);
+}
+
+/* This fine tunes the HT link settings, which were loaded by ROM strap. */
+static void host_ctrl_enable_k8m890(struct device *dev) {
+
+	/*
+	 * Set PCI to HT outstanding requests to 03.
+	 * Bit 4 32 AGP ADS Read Outstanding Request Number
+	 */
+	pci_write_config8(dev, 0xa0, 0x13);
+
+	/*
+	 * NVRAM I/O base at K8T890_NVRAM_IO_BASE
+	 */
+
+	pci_write_config8(dev, 0xa2, (K8T890_NVRAM_IO_BASE >> 8));
+
+	/* Enable NVRAM and enable non-posted PCI writes. */
+	pci_write_config8(dev, 0xa1, 0x8f);
+
+	/* Arbitration control  */
+	pci_write_config8(dev, 0xa5, 0x3c);
+
+	/* Arbitration control 2, Enable C2NOW delay to PSTATECTL */
+	pci_write_config8(dev, 0xa6, 0x83);
+
+}
+#if 0
+struct cbmem_entry *get_cbmem_toc(void) {
+		return (struct cbmem_entry *) inl(K8T890_NVRAM_IO_BASE+K8T890_NVRAM_CBMEM_TOC);
+}
+#endif
+void set_cbmem_toc(struct cbmem_entry *toc) {
+		outl((u32) toc, K8T890_NVRAM_IO_BASE+K8T890_NVRAM_CBMEM_TOC);
+}
+
+static const struct device_operations host_ctrl_ops_t = {
+	.read_resources		= pci_dev_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.enable			= host_ctrl_enable_k8t890,
+	.ops_pci		= 0,
+};
+
+static const struct device_operations host_ctrl_ops_m = {
+	.read_resources		= pci_dev_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.enable			= host_ctrl_enable_k8m890,
+	.ops_pci		= 0,
+};
+
+static const struct pci_driver northbridge_driver_t __pci_driver = {
+	.ops	= &host_ctrl_ops_t,
+	.vendor	= PCI_VENDOR_ID_VIA,
+	.device	= PCI_DEVICE_ID_VIA_K8T890CE_2,
+};
+
+static const struct pci_driver northbridge_driver_m __pci_driver = {
+	.ops	= &host_ctrl_ops_m,
+	.vendor	= PCI_VENDOR_ID_VIA,
+	.device	= PCI_DEVICE_ID_VIA_K8M890CE_2,
+};