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author | Rudolf Marek <r.marek@assembler.cz> | 2008-09-19 22:58:59 +0000 |
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committer | Rudolf Marek <r.marek@assembler.cz> | 2008-09-19 22:58:59 +0000 |
commit | 0b0771d180d5b18a3d698ccac54449112a9fca91 (patch) | |
tree | df7be41b042262a4ac04f72b48ff61c71df5e0e7 /src/southbridge/via/k8t890/k8t890_dram.c | |
parent | c4128cfbec0d496873b9a2a684cf32a23b17137d (diff) | |
download | coreboot-0b0771d180d5b18a3d698ccac54449112a9fca91.tar.gz coreboot-0b0771d180d5b18a3d698ccac54449112a9fca91.tar.bz2 coreboot-0b0771d180d5b18a3d698ccac54449112a9fca91.zip |
Attached patch fixes at least one issue ;) During the PCI BAR sizing must be the
D1F0 bridge without activated I/O and MEM resources, otherwise it will hang
whole PCI bus.
U-boot is also disabling the IO/MEM decode when sizing the BARs, dont know why
does we not.
Second small change just changes a bit which controls the PSTATECTL logic.
Third change deals with the integrated VGA, which needs to be enabled early,
so the VGA_EN is set along the bridges, and PCI K8 resource maps are set
correctly. Finally the CPU accessible framebuffer is now disabled as it is not
needed.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3587 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/via/k8t890/k8t890_dram.c')
-rw-r--r-- | src/southbridge/via/k8t890/k8t890_dram.c | 23 |
1 files changed, 13 insertions, 10 deletions
diff --git a/src/southbridge/via/k8t890/k8t890_dram.c b/src/southbridge/via/k8t890/k8t890_dram.c index 00e5fa5f24ed..1c60a78a1393 100644 --- a/src/southbridge/via/k8t890/k8t890_dram.c +++ b/src/southbridge/via/k8t890/k8t890_dram.c @@ -63,6 +63,15 @@ static void dram_enable(struct device *dev) /* The Address Next to the Last Valid DRAM Address */ pci_write_config16(dev, 0x88, (msr.lo >> 24) | reg); + +} + +static void dram_enable_k8m890(struct device *dev) +{ + dram_enable(dev); + + /* enable VGA, so the bridges gets VGA_EN and resources are set */ + pci_write_config8(dev, 0xa1, 0x80); } static struct resource *resmax; @@ -113,17 +122,11 @@ static void dram_init_fb(struct device *dev) printk_debug("VIA FB proposed base: %llx\n", proposed_base); - /* enable UMA but no FB */ + /* Step 1: enable UMA but no FB */ pci_write_config8(dev, 0xa1, 0x80); - /* 27:21 goes to 7:1, 0 is enable CPU access */ - tmp = (proposed_base >> 20) | 0x1; - pci_write_config8(dev, 0xa0, tmp); - - /* 31:28 goes to 3:0 */ - tmp = ((proposed_base >> 28) & 0xf); - tmp = ((log2(K8M890_FBSIZEMB) - 2) << 4); - tmp |= 0x80; + /* Step 2: enough is just the FB size, the CPU accessible address is not needed */ + tmp = ((log2(K8M890_FBSIZEMB) - 2) << 4) | 0x80; pci_write_config8(dev, 0xa1, tmp); /* TODO K8 needs some UMA fine tuning too maybe call some generic routine here? */ @@ -141,7 +144,7 @@ static const struct device_operations dram_ops_m = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .enable = dram_enable, + .enable = dram_enable_k8m890, .init = dram_init_fb, .ops_pci = 0, }; |