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| author | Angel Pons <th3fanbus@gmail.com> | 2021-06-05 12:34:23 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-06-07 11:34:11 +0000 |
| commit | 023968453e13f09420c8d6ecdeeb42a229c0ff09 (patch) | |
| tree | 072bece04599c898875992aae35e8d4b6005a7e7 /src/southbridge | |
| parent | d047927168e63004d0b4fa521b48d321af1b0ac6 (diff) | |
| download | coreboot-023968453e13f09420c8d6ecdeeb42a229c0ff09.tar.gz coreboot-023968453e13f09420c8d6ecdeeb42a229c0ff09.tar.bz2 coreboot-023968453e13f09420c8d6ecdeeb42a229c0ff09.zip | |
sb/intel/bd82x6x: Use array for PCIe ASPM overrides
Using an array reduces the amount of boilerplate code.
Change-Id: Ic6a48a01d3b96e69273dc28bdb6699ce7c0931b2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55246
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/chip.h | 9 | ||||
| -rw-r--r-- | src/southbridge/intel/bd82x6x/pcie.c | 27 |
2 files changed, 2 insertions, 34 deletions
diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h index 45f1226bdcab..ac299440702e 100644 --- a/src/southbridge/intel/bd82x6x/chip.h +++ b/src/southbridge/intel/bd82x6x/chip.h @@ -61,14 +61,7 @@ struct southbridge_intel_bd82x6x_config { uint8_t pcie_port_coalesce; /* Override PCIe ASPM */ - uint8_t pcie_aspm_f0; - uint8_t pcie_aspm_f1; - uint8_t pcie_aspm_f2; - uint8_t pcie_aspm_f3; - uint8_t pcie_aspm_f4; - uint8_t pcie_aspm_f5; - uint8_t pcie_aspm_f6; - uint8_t pcie_aspm_f7; + uint8_t pcie_aspm[8]; int c2_latency; int docking_supported; diff --git a/src/southbridge/intel/bd82x6x/pcie.c b/src/southbridge/intel/bd82x6x/pcie.c index 851339082859..399c73aebcef 100644 --- a/src/southbridge/intel/bd82x6x/pcie.c +++ b/src/southbridge/intel/bd82x6x/pcie.c @@ -162,32 +162,7 @@ static void pch_pcie_pm_late(struct device *dev) pci_or_config32(dev, 0xd4, 1 << 1); /* Check for a rootport ASPM override */ - switch (PCI_FUNC(dev->path.pci.devfn)) { - case 0: - apmc = config->pcie_aspm_f0; - break; - case 1: - apmc = config->pcie_aspm_f1; - break; - case 2: - apmc = config->pcie_aspm_f2; - break; - case 3: - apmc = config->pcie_aspm_f3; - break; - case 4: - apmc = config->pcie_aspm_f4; - break; - case 5: - apmc = config->pcie_aspm_f5; - break; - case 6: - apmc = config->pcie_aspm_f6; - break; - case 7: - apmc = config->pcie_aspm_f7; - break; - } + apmc = config->pcie_aspm[PCI_FUNC(dev->path.pci.devfn)]; /* Setup the override or get the real ASPM setting */ if (apmc) { |