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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-10-12 10:54:30 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-10-18 12:51:26 +0000 |
| commit | 400ce55566caa541304b2483e61bcc2df941998c (patch) | |
| tree | 4e0cbf4aef7fb00a9c40327075ffa9737e56b104 /src/southbridge | |
| parent | e64a585374de88ea896ed517445a34986aa321b9 (diff) | |
| download | coreboot-400ce55566caa541304b2483e61bcc2df941998c.tar.gz coreboot-400ce55566caa541304b2483e61bcc2df941998c.tar.bz2 coreboot-400ce55566caa541304b2483e61bcc2df941998c.zip | |
cpu/amd: Use common AMD's MSR
Phase 1. Due to the size of the effort, this CL is broken into several
phases.
Change-Id: I0236e0960cd1e79558ea50c814e1de2830aa0550
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/amd/rs780/early_setup.c | 5 | ||||
| -rw-r--r-- | src/southbridge/amd/sr5650/early_setup.c | 5 | ||||
| -rw-r--r-- | src/southbridge/amd/sr5650/sr5650.c | 3 |
3 files changed, 8 insertions, 5 deletions
diff --git a/src/southbridge/amd/rs780/early_setup.c b/src/southbridge/amd/rs780/early_setup.c index ab75e5f57ffc..865b577279af 100644 --- a/src/southbridge/amd/rs780/early_setup.c +++ b/src/southbridge/amd/rs780/early_setup.c @@ -18,6 +18,7 @@ #include <northbridge/amd/amdmct/mct/mct_d.h> #include <console/console.h> #include <cpu/x86/msr.h> +#include <cpu/amd/msr.h> #include "rev.h" #include "rs780.h" @@ -317,10 +318,10 @@ static void k8_optimization(void) set_nbcfg_enable_bits(k8_f2, 0xA0, 3 << 2, 3 << 2); set_nbcfg_enable_bits(k8_f2, 0xA0, 1 << 5, 1 << 5); - msr = rdmsr(0xC001001F); + msr = rdmsr(NB_CFG_MSR); msr.lo &= ~(1 << 9); msr.hi &= ~(1 << 4); - wrmsr(0xC001001F, msr); + wrmsr(NB_CFG_MSR, msr); } #else #define k8_optimization() do {} while (0) diff --git a/src/southbridge/amd/sr5650/early_setup.c b/src/southbridge/amd/sr5650/early_setup.c index 96adfb5bdd29..543cb0efbf54 100644 --- a/src/southbridge/amd/sr5650/early_setup.c +++ b/src/southbridge/amd/sr5650/early_setup.c @@ -20,6 +20,7 @@ #include <arch/io.h> #include <console/console.h> #include <cpu/x86/msr.h> +#include <cpu/amd/msr.h> #include <option.h> #include <reset.h> #include "sr5650.h" @@ -309,9 +310,9 @@ void fam10_optimization(void) return; printk(BIOS_INFO, "fam10_optimization()\n"); - msr = rdmsr(0xC001001F); + msr = rdmsr(NB_CFG_MSR); msr.hi |= 1 << 14; /* bit 46: EnableCf8ExtCfg */ - wrmsr(0xC001001F, msr); + wrmsr(NB_CFG_MSR, msr); cpu_f0 = PCI_DEV(0, 0x18, 0); cpu_f2 = PCI_DEV(0, 0x18, 2); diff --git a/src/southbridge/amd/sr5650/sr5650.c b/src/southbridge/amd/sr5650/sr5650.c index 1c2fe48407ee..1e85c4898605 100644 --- a/src/southbridge/amd/sr5650/sr5650.c +++ b/src/southbridge/amd/sr5650/sr5650.c @@ -22,6 +22,7 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <cpu/x86/msr.h> +#include <cpu/amd/msr.h> #include <cpu/amd/mtrr.h> #include <stdlib.h> #include <delay.h> @@ -40,7 +41,7 @@ struct resource *sr5650_retrieve_cpu_mmio_resource() for (domain = all_devices; domain; domain = domain->next) { if (domain->bus->dev->path.type != DEVICE_PATH_DOMAIN) continue; - res = probe_resource(domain->bus->dev, 0xc0010058); + res = probe_resource(domain->bus->dev, MMIO_CONF_BASE); if (res) return res; } |