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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-12-19 06:45:56 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2022-11-11 12:42:34 +0000 |
| commit | 458751c2d5b5ebfdaa4397be44b2ac6a7fd9c8dc (patch) | |
| tree | 48377137abfcf0b7760497e442e27ca9373499d9 /src/southbridge | |
| parent | a83c502d5a0a889b9ccd9ed053bad5b3060a4314 (diff) | |
| download | coreboot-458751c2d5b5ebfdaa4397be44b2ac6a7fd9c8dc.tar.gz coreboot-458751c2d5b5ebfdaa4397be44b2ac6a7fd9c8dc.tar.bz2 coreboot-458751c2d5b5ebfdaa4397be44b2ac6a7fd9c8dc.zip | |
aopen/dxplplusu: Add early GPIO settings
Required for 2nd COM port to work.
Change-Id: Ib211e9c4b487fadec3d3487f9d745f44d8ca4579
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52815
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/intel/i82801dx/i82801dx.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/southbridge/intel/i82801dx/i82801dx.h b/src/southbridge/intel/i82801dx/i82801dx.h index e63327c01e47..c07e5812fd26 100644 --- a/src/southbridge/intel/i82801dx/i82801dx.h +++ b/src/southbridge/intel/i82801dx/i82801dx.h @@ -71,6 +71,7 @@ void i82801dx_early_init(void); #define PIRQG_ROUT 0x6A #define PIRQH_ROUT 0x6B #define COM_DEC 0xE0 +#define GEN1_DEC 0xE4 #define LPC_EN 0xE6 #define FUNC_DIS 0xF2 |