diff options
| author | Tristan Shieh <tristan.shieh@mediatek.com> | 2018-06-06 13:35:12 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-06-07 11:08:17 +0000 |
| commit | 4c8d4872a56ea99feb3397619927db360b2f6339 (patch) | |
| tree | 3d5572dd58e7f88d8fe86592f33259285213f06e /src/southbridge | |
| parent | f42db110d0174f05745e3558067d114eae37825b (diff) | |
| download | coreboot-4c8d4872a56ea99feb3397619927db360b2f6339.tar.gz coreboot-4c8d4872a56ea99feb3397619927db360b2f6339.tar.bz2 coreboot-4c8d4872a56ea99feb3397619927db360b2f6339.zip | |
mediatek: Refactor to sharing code among similar SOCs
This patch refactor cbmem and timer code which will be reused among
similar SOCs.
BUG=b:80501386
BRANCH=none
TEST=the refactored code works fine on the new platform (with the rest
of the patches applied) and Elm platform
Change-Id: I397ebdc0c97c7616bd547022d2ce2a8f08f3c232
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/26881
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge')
0 files changed, 0 insertions, 0 deletions