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| author | Patrick Rudolph <patrick.rudolph@9elements.com> | 2023-10-03 11:35:15 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-10-12 12:41:00 +0000 |
| commit | 653459016d9fc6f13532e4bc9d52f98918602739 (patch) | |
| tree | ea2ce31bee5a353abdd353e149cddc78e2e0dd59 /src/southbridge | |
| parent | 2fcef78ff84c184f7a9dd0e007c95b56cda552f5 (diff) | |
| download | coreboot-653459016d9fc6f13532e4bc9d52f98918602739.tar.gz coreboot-653459016d9fc6f13532e4bc9d52f98918602739.tar.bz2 coreboot-653459016d9fc6f13532e4bc9d52f98918602739.zip | |
sb/intel/bd82x6x/pch: Mark static devices hidden
Because integrated PCI devices are hidden in chip_ops
the PCI enumeration code never sees them.
When hiding static devices mark them as hidden so the
PCI enumeration no longer complains about them being
missing, even though they are present and were working
just fine.
Test: Disabled southbridge devices no longer appear in
"Leftover static devices:" log.
Change-Id: Iae70072a85b62a456102190a5f72f4d652ad6d5a
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78230
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/pch.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c index c668f9a6b9a9..a7ab83a24b1c 100644 --- a/src/southbridge/intel/bd82x6x/pch.c +++ b/src/southbridge/intel/bd82x6x/pch.c @@ -131,6 +131,10 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue) /* Set bit in function disable register to hide this device */ static void pch_hide_devfn(unsigned int devfn) { + struct device *dev = pcidev_path_on_root(devfn); + if (dev) + dev->hidden = true; + switch (devfn) { case PCI_DEVFN(20, 0): /* xHCI */ if (pch_silicon_type() == PCH_TYPE_PPT) { |