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| author | Patrick Rudolph <patrick.rudolph@9elements.com> | 2023-10-02 07:06:45 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-10-09 13:56:56 +0000 |
| commit | 873178bfd64fe98558cc50e35977c7cc380374d5 (patch) | |
| tree | ea83ed1735850ae31f4b6e3ae841f562afd800d9 /src/southbridge | |
| parent | a9b3cf3358a2df3038566b3712741ee5763206bb (diff) | |
| download | coreboot-873178bfd64fe98558cc50e35977c7cc380374d5.tar.gz coreboot-873178bfd64fe98558cc50e35977c7cc380374d5.tar.bz2 coreboot-873178bfd64fe98558cc50e35977c7cc380374d5.zip | |
sb/intel/bd82x6x: Follow PCH BIOS spec
PCH BIOS spec says that BIOS must clear BIT26 in register 0x338
in PEI, as done on lynxpoint.
Copy and adapt the lynxpoint code to do the same on bd82x6x.
Add special case for UM77 chipset, which only has 4 PCIe ports.
Test: System still boots and all PCIe ports are fully working.
Change-Id: I865818c0c22194fffcb2bbdf8c43737b0dce2307
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78225
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/early_pch.c | 8 | ||||
| -rw-r--r-- | src/southbridge/intel/bd82x6x/pch.h | 5 |
2 files changed, 12 insertions, 1 deletions
diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c index e4e002d80563..8433bb2dd548 100644 --- a/src/southbridge/intel/bd82x6x/early_pch.c +++ b/src/southbridge/intel/bd82x6x/early_pch.c @@ -17,6 +17,7 @@ #include "chip.h" #define SOUTHBRIDGE PCI_DEV(0, 0x1f, 0) +#define PCI_DEVICE_ID_INTEL_UM77 0x1e58 static void wait_iobp(void) { @@ -135,8 +136,15 @@ void early_pch_init_native_dmi_post(void) void early_pch_init_native(void) { + const u16 dev_id = pci_read_config16(PCH_LPC_DEV, PCI_DEVICE_ID); + u8 pcie_ports = (dev_id == PCI_DEVICE_ID_INTEL_UM77) ? 4 : 8; + pci_write_config8(SOUTHBRIDGE, 0xa6, pci_read_config8(SOUTHBRIDGE, 0xa6) | 2); + /* Clear this bit early for PCIe device detection */ + for (uint8_t i = 0; i < pcie_ports; i++) + pci_update_config32(PCH_PCIE_DEV(i), 0x338, ~(1 << 26), 0); + RCBA32(CIR1) = 0x00109000; RCBA32(REC); // !!! = 0x00000000 RCBA32(REC) = 0x40000000; diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 8face0649ebe..6d164ead42a9 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -74,12 +74,15 @@ void early_usb_init(const struct southbridge_usb_port *portmap); #define PCH_EHCI2_DEV PCI_DEV(0, 0x1a, 0) #define PCH_ME_DEV PCI_DEV(0, 0x16, 0) #define PCH_THERMAL_DEV PCI_DEV(0, 0x1f, 6) -#define PCH_PCIE_DEV_SLOT 28 #define PCH_IOAPIC_PCI_BUS 250 #define PCH_IOAPIC_PCI_SLOT 31 #define PCH_HPET_PCI_BUS 250 #define PCH_HPET_PCI_SLOT 15 +/* PCI Configuration Space (D28:F0): PCI2PCI */ +#define PCH_PCIE_DEV_SLOT 28 +#define PCH_PCIE_DEV(_func) PCI_DEV(0, PCH_PCIE_DEV_SLOT, _func) + /* PCI Configuration Space (D20:F0): xHCI */ #define PCH_XHCI_DEV PCI_DEV(0, 0x14, 0) |