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| author | Nico Huber <nico.h@gmx.de> | 2019-07-20 17:03:56 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-07-20 15:27:01 +0000 |
| commit | ae317695e3f03d55fbba1805ff06e004383e67c8 (patch) | |
| tree | 043aa5f7b46a16df85322a3c38071b0eaa428422 /src/southbridge | |
| parent | 0db6e7569da8aff8d868afd65027c075b4710fa4 (diff) | |
| download | coreboot-ae317695e3f03d55fbba1805ff06e004383e67c8.tar.gz coreboot-ae317695e3f03d55fbba1805ff06e004383e67c8.tar.bz2 coreboot-ae317695e3f03d55fbba1805ff06e004383e67c8.zip | |
mb/,sb/intel/i82801gx: Merge `ide_legacy_combined` into `sata_mode`4.10
Functional changes were already done in 5eb81bed2e (sb/intel/i82801gx:
Detect if the southbridge supports AHCI) but we forgot to update the
`chip.h` and devicetrees.
Change-Id: I0e25f54ead8f5bbc6041d31347038e800787b624
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34462
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/intel/i82801gx/chip.h | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/southbridge/intel/i82801gx/chip.h b/src/southbridge/intel/i82801gx/chip.h index 8909f50bc12e..4e78c30db247 100644 --- a/src/southbridge/intel/i82801gx/chip.h +++ b/src/southbridge/intel/i82801gx/chip.h @@ -68,7 +68,6 @@ struct southbridge_intel_i82801gx_config { uint16_t alt_gp_smi_en; /* IDE configuration */ - uint32_t ide_legacy_combined; uint32_t ide_enable_primary; uint32_t ide_enable_secondary; enum sata_mode sata_mode; |