diff options
author | Subrata Banik <subrata.banik@intel.com> | 2019-11-01 18:26:56 +0530 |
---|---|---|
committer | Subrata Banik <subrata.banik@intel.com> | 2019-11-09 03:26:54 +0000 |
commit | b8df689a6aaaa721103ed75d647decad2b4a9528 (patch) | |
tree | a0400af4e37c1c1a777f3e66cb16d46ac6a307d7 /src/southbridge | |
parent | 91e89c5393535406f98f0f05354459a123f0885b (diff) | |
download | coreboot-b8df689a6aaaa721103ed75d647decad2b4a9528.tar.gz coreboot-b8df689a6aaaa721103ed75d647decad2b4a9528.tar.bz2 coreboot-b8df689a6aaaa721103ed75d647decad2b4a9528.zip |
soc/intel/tigerlake/acpi: Copy acpi directory from icelake
Clone entirely from Icelake
List of changes on top off initial icelake clone
1. Removed Descriptor Name for Memory mapped SPI flash and
local APIC in northbridge.asl
2. Rearranged code in gpio.asl to move RBUF object under _CRS
and made the file use ASL2.0 syntax.
3. Make use of absolute path for scs.asl
4. Remove unused smbus.asl
5. Rearranged code in nothbridge.asl to move MCRS object under _CRS,
use absolute variable path and added TODO for further clean up.
6. Refer absolute variable path in scs.asl
Change-Id: If967cb5904f543ce21eb6e89421df0e5673d2238
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36553
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Diffstat (limited to 'src/southbridge')
0 files changed, 0 insertions, 0 deletions