diff options
| author | Patrick Rudolph <patrick.rudolph@9elements.com> | 2023-11-04 11:08:25 +0100 |
|---|---|---|
| committer | Shelley Chen <shchen@google.com> | 2023-12-26 17:03:56 +0000 |
| commit | b95ef282ff785f63ce2a74ff0140072856893687 (patch) | |
| tree | c25cd42c3594c53ac809eb8b307fd835a1a55c7d /src/southbridge | |
| parent | f20c355a1f7b22c8d8540318c5137e438538d63e (diff) | |
| download | coreboot-b95ef282ff785f63ce2a74ff0140072856893687.tar.gz coreboot-b95ef282ff785f63ce2a74ff0140072856893687.tar.bz2 coreboot-b95ef282ff785f63ce2a74ff0140072856893687.zip | |
sb/intel/bd82x6x/pch: Add method to identify PCH
Identify PCH type by LPC device ID. This allows to identify
the PCH without including northbridge headers.
Tested: Lenovo X220 still boots.
Change-Id: Ic3e15c1d8d4b1d1012d6204cc65de92d91431fbe
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79145
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/common.c | 21 | ||||
| -rw-r--r-- | src/southbridge/intel/bd82x6x/pch.h | 1 |
2 files changed, 22 insertions, 0 deletions
diff --git a/src/southbridge/intel/bd82x6x/common.c b/src/southbridge/intel/bd82x6x/common.c index f4c757a0609b..7163d3edc7bd 100644 --- a/src/southbridge/intel/bd82x6x/common.c +++ b/src/southbridge/intel/bd82x6x/common.c @@ -32,6 +32,27 @@ int pch_silicon_type(void) return pch_type; } +bool pch_is_mobile(void) +{ + const u16 devids[] = { + PCI_DID_INTEL_6_SERIES_MOBILE_SFF, PCI_DID_INTEL_6_SERIES_MOBILE, + PCI_DID_INTEL_6_SERIES_UM67, PCI_DID_INTEL_6_SERIES_HM65, + PCI_DID_INTEL_6_SERIES_HM67, PCI_DID_INTEL_6_SERIES_QS67, + PCI_DID_INTEL_6_SERIES_QM67, + PCI_DID_INTEL_7_SERIES_MOBILE, PCI_DID_INTEL_7_SERIES_MOBILE_SFF, + PCI_DID_INTEL_7_SERIES_QM77, PCI_DID_INTEL_7_SERIES_QS77, + PCI_DID_INTEL_7_SERIES_HM77, PCI_DID_INTEL_7_SERIES_UM77, + PCI_DID_INTEL_7_SERIES_HM76, PCI_DID_INTEL_7_SERIES_HM75, + PCI_DID_INTEL_7_SERIES_HM70, PCI_DID_INTEL_7_SERIES_NM70 + }; + u16 devid = pci_s_read_config16(PCH_LPC_DEV, PCI_DEVICE_ID); + + for (size_t i = 0; i < ARRAY_SIZE(devids); i++) + if (devid == devids[i]) + return true; + return false; +} + int pch_silicon_supported(int type, int rev) { int cur_type = pch_silicon_type(); diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 3bb8701e5cf9..88c8df5c4a25 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -35,6 +35,7 @@ int pch_silicon_revision(void); int pch_silicon_type(void); int pch_silicon_supported(int type, int rev); +bool pch_is_mobile(void); void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); void enable_usb_bar(void); |