summaryrefslogtreecommitdiffstats
path: root/src/southbridge
diff options
context:
space:
mode:
authorFelix Held <felix-coreboot@felixheld.de>2023-03-24 22:07:48 +0100
committerFelix Held <felix-coreboot@felixheld.de>2023-03-29 13:24:17 +0000
commitc08d804f01d88ac028c7271f0efed07373c3bc97 (patch)
tree0eabe66f9ddee3089803ebf30bf81a2ed463067a /src/southbridge
parent77c5d898aecbb15b37e4458cd32ca95f10e2264e (diff)
downloadcoreboot-c08d804f01d88ac028c7271f0efed07373c3bc97.tar.gz
coreboot-c08d804f01d88ac028c7271f0efed07373c3bc97.tar.bz2
coreboot-c08d804f01d88ac028c7271f0efed07373c3bc97.zip
soc/amd/stoneyridge/monotonic_time: add comment that we can't use TSC
Due to a non-constant TSC rate before the microcode update is applied, the Performance Time Stamp Counter is used instead. To clarify this, add a comment to the timestamp_get implementation. See commit 24079323d4d8 ("soc/amd/stoneyridge: provide alternate monotonic timer") and the description of the TscInvariant bit in CPUID Fn8000_0007_EDX Advanced Power Management Information in the public version of BKDG #55072 Rev 3.09 for more details. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I824b372c36fa6f3eb912469b235a9474f6a58ff5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74018 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Diffstat (limited to 'src/southbridge')
0 files changed, 0 insertions, 0 deletions