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| author | Angel Pons <th3fanbus@gmail.com> | 2021-03-18 20:35:19 +0100 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2021-03-22 13:01:19 +0000 |
| commit | c1301dd2d23532d4d824499a6632fa2d08fb23e5 (patch) | |
| tree | e961776e1793d91b9cbf5f5a527cfc057db76020 /src/southbridge | |
| parent | 1895d1a181a0e50f05f03c247d9827e976b9b333 (diff) | |
| download | coreboot-c1301dd2d23532d4d824499a6632fa2d08fb23e5.tar.gz coreboot-c1301dd2d23532d4d824499a6632fa2d08fb23e5.tar.bz2 coreboot-c1301dd2d23532d4d824499a6632fa2d08fb23e5.zip | |
{lynxpoint/broadwell}: Set Azalia HDCFG.BCLD bit
Lock down several HD Audio registers by setting the HDCFG.BCLD bit.
Tested on Asrock B85M Pro4, the GCAP register becomes read-only.
Change-Id: Id6208289a68baaedc4aad51cc0c5355f996a1b00
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51645
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/intel/lynxpoint/azalia.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/southbridge/intel/lynxpoint/azalia.c b/src/southbridge/intel/lynxpoint/azalia.c index ad84b0093a0c..27ee9248a289 100644 --- a/src/southbridge/intel/lynxpoint/azalia.c +++ b/src/southbridge/intel/lynxpoint/azalia.c @@ -121,11 +121,18 @@ static void azalia_init(struct device *dev) } } +static void azalia_final(struct device *dev) +{ + /* Set HDCFG.BCLD */ + pci_or_config16(dev, 0x40, 1 << 1); +} + static struct device_operations azalia_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = azalia_init, + .final = azalia_final, .ops_pci = &pci_dev_ops_pci, }; |