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author | Patrick Georgi <pgeorgi@chromium.org> | 2015-03-27 13:50:11 +0100 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2015-03-28 19:14:47 +0100 |
commit | ea9f30801822716349772157e12d943b11975521 (patch) | |
tree | adbe4249e2260612337e7f15f0de5dd4bb25a5a0 /src/southbridge | |
parent | 276ff99a079b096f47863ae2cf5a5336601c1522 (diff) | |
download | coreboot-ea9f30801822716349772157e12d943b11975521.tar.gz coreboot-ea9f30801822716349772157e12d943b11975521.tar.bz2 coreboot-ea9f30801822716349772157e12d943b11975521.zip |
build system: normalize linker script file names
We have .lb, .lds, and .ld in the tree. Go for .ld everywhere.
This is inspired by the commit listed below, but rewritten to match
upstream, and split in smaller pieces to keep intent clear.
Change-Id: I3126af608afe4937ec4551a78df5a7824e09b04b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Based-On-Change-Id: I50af7dacf616e0f8ff4c43f4acc679089ad7022b
Based-On-Signed-off-by: Julius Werner <jwerner@chromium.org>
Based-On-Reviewed-on: https://chromium-review.googlesource.com/219170
Reviewed-on: http://review.coreboot.org/9107
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/southbridge')
-rw-r--r-- | src/southbridge/nvidia/ck804/Makefile.inc | 2 | ||||
-rw-r--r-- | src/southbridge/nvidia/ck804/nic.c | 2 | ||||
-rw-r--r-- | src/southbridge/nvidia/ck804/romstrap.ld (renamed from src/southbridge/nvidia/ck804/romstrap.lds) | 0 | ||||
-rw-r--r-- | src/southbridge/nvidia/mcp55/Makefile.inc | 2 | ||||
-rw-r--r-- | src/southbridge/nvidia/mcp55/nic.c | 2 | ||||
-rw-r--r-- | src/southbridge/nvidia/mcp55/romstrap.ld (renamed from src/southbridge/nvidia/mcp55/romstrap.lds) | 0 | ||||
-rw-r--r-- | src/southbridge/sis/sis966/Makefile.inc | 2 | ||||
-rw-r--r-- | src/southbridge/sis/sis966/romstrap.ld (renamed from src/southbridge/sis/sis966/romstrap.lds) | 0 | ||||
-rw-r--r-- | src/southbridge/via/k8t890/Makefile.inc | 2 | ||||
-rw-r--r-- | src/southbridge/via/k8t890/romstrap.ld (renamed from src/southbridge/via/k8t890/romstrap.lds) | 0 |
10 files changed, 6 insertions, 6 deletions
diff --git a/src/southbridge/nvidia/ck804/Makefile.inc b/src/southbridge/nvidia/ck804/Makefile.inc index db145d08a831..dacfc9c8c5dd 100644 --- a/src/southbridge/nvidia/ck804/Makefile.inc +++ b/src/southbridge/nvidia/ck804/Makefile.inc @@ -20,4 +20,4 @@ ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c romstage-y += early_smbus.c chipset_bootblock_inc += $(src)/southbridge/nvidia/ck804/romstrap.inc -chipset_bootblock_lds += $(src)/southbridge/nvidia/ck804/romstrap.lds +chipset_bootblock_lds += $(src)/southbridge/nvidia/ck804/romstrap.ld diff --git a/src/southbridge/nvidia/ck804/nic.c b/src/southbridge/nvidia/ck804/nic.c index b827dcffd44a..1207a95419dd 100644 --- a/src/southbridge/nvidia/ck804/nic.c +++ b/src/southbridge/nvidia/ck804/nic.c @@ -90,7 +90,7 @@ static void nic_init(struct device *dev) /* If that is invalid we will read that from romstrap. */ if (!eeprom_valid) { u32 *mac_pos; - mac_pos = (u32 *)0xffffffd0; /* See romstrap.inc and romstrap.lds. */ + mac_pos = (u32 *)0xffffffd0; /* See romstrap.inc and romstrap.ld. */ mac_l = read32(mac_pos) + nic_index; mac_h = read32(mac_pos + 1); } diff --git a/src/southbridge/nvidia/ck804/romstrap.lds b/src/southbridge/nvidia/ck804/romstrap.ld index 4d7996f771a4..4d7996f771a4 100644 --- a/src/southbridge/nvidia/ck804/romstrap.lds +++ b/src/southbridge/nvidia/ck804/romstrap.ld diff --git a/src/southbridge/nvidia/mcp55/Makefile.inc b/src/southbridge/nvidia/mcp55/Makefile.inc index 03a34eb71caf..b4dc460b592b 100644 --- a/src/southbridge/nvidia/mcp55/Makefile.inc +++ b/src/southbridge/nvidia/mcp55/Makefile.inc @@ -19,4 +19,4 @@ romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c chipset_bootblock_inc += $(src)/southbridge/nvidia/mcp55/romstrap.inc -chipset_bootblock_lds += $(src)/southbridge/nvidia/mcp55/romstrap.lds +chipset_bootblock_lds += $(src)/southbridge/nvidia/mcp55/romstrap.ld diff --git a/src/southbridge/nvidia/mcp55/nic.c b/src/southbridge/nvidia/mcp55/nic.c index 136d060d0b19..d8f691af1401 100644 --- a/src/southbridge/nvidia/mcp55/nic.c +++ b/src/southbridge/nvidia/mcp55/nic.c @@ -162,7 +162,7 @@ static void nic_init(struct device *dev) // if that is invalid we will read that from romstrap if(!eeprom_valid) { u32 *mac_pos; - mac_pos = (u32 *)0xffffffd0; // refer to romstrap.inc and romstrap.lds + mac_pos = (u32 *)0xffffffd0; // refer to romstrap.inc and romstrap.ld mac_l = read32(mac_pos) + nic_index; // overflow? mac_h = read32(mac_pos + 1); diff --git a/src/southbridge/nvidia/mcp55/romstrap.lds b/src/southbridge/nvidia/mcp55/romstrap.ld index 784e7d5f0f38..784e7d5f0f38 100644 --- a/src/southbridge/nvidia/mcp55/romstrap.lds +++ b/src/southbridge/nvidia/mcp55/romstrap.ld diff --git a/src/southbridge/sis/sis966/Makefile.inc b/src/southbridge/sis/sis966/Makefile.inc index 1a9ea65429d7..5c696222d947 100644 --- a/src/southbridge/sis/sis966/Makefile.inc +++ b/src/southbridge/sis/sis966/Makefile.inc @@ -14,4 +14,4 @@ romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c chipset_bootblock_inc += $(src)/southbridge/sis/sis966/romstrap.inc -chipset_bootblock_lds += $(src)/southbridge/sis/sis966/romstrap.lds +chipset_bootblock_lds += $(src)/southbridge/sis/sis966/romstrap.ld diff --git a/src/southbridge/sis/sis966/romstrap.lds b/src/southbridge/sis/sis966/romstrap.ld index 784e7d5f0f38..784e7d5f0f38 100644 --- a/src/southbridge/sis/sis966/romstrap.lds +++ b/src/southbridge/sis/sis966/romstrap.ld diff --git a/src/southbridge/via/k8t890/Makefile.inc b/src/southbridge/via/k8t890/Makefile.inc index 6d9407d03bb5..1c5ff3fefabc 100644 --- a/src/southbridge/via/k8t890/Makefile.inc +++ b/src/southbridge/via/k8t890/Makefile.inc @@ -9,4 +9,4 @@ ramstage-y += error.c ramstage-y += chrome.c chipset_bootblock_inc += $(src)/southbridge/via/k8t890/romstrap.inc -chipset_bootblock_lds += $(src)/southbridge/via/k8t890/romstrap.lds +chipset_bootblock_lds += $(src)/southbridge/via/k8t890/romstrap.ld diff --git a/src/southbridge/via/k8t890/romstrap.lds b/src/southbridge/via/k8t890/romstrap.ld index 235769d0c9ca..235769d0c9ca 100644 --- a/src/southbridge/via/k8t890/romstrap.lds +++ b/src/southbridge/via/k8t890/romstrap.ld |