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| author | Felix Singer <felixsinger@posteo.net> | 2024-01-12 21:21:06 +0100 |
|---|---|---|
| committer | Felix Singer <service+coreboot-gerrit@felixsinger.de> | 2024-01-14 10:15:34 +0000 |
| commit | f4842bbc145da72c37321fed876b3140f79c6aa7 (patch) | |
| tree | a62832fe92d0e5904a86837d22a041a5f49d49d4 /src/southbridge | |
| parent | d04378118d17abaf82cf03a9fd4abcfeb917badc (diff) | |
| download | coreboot-f4842bbc145da72c37321fed876b3140f79c6aa7.tar.gz coreboot-f4842bbc145da72c37321fed876b3140f79c6aa7.tar.bz2 coreboot-f4842bbc145da72c37321fed876b3140f79c6aa7.zip | |
sb/intel: Use boolean for pcie_hotplug_map attribute
Change-Id: Ia5e1ee683fa3d8d216ece26426e9870981ede2ba
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79932
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/chip.h | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/common/pciehp.c | 3 | ||||
| -rw-r--r-- | src/southbridge/intel/common/pciehp.h | 4 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801ix/chip.h | 3 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801jx/chip.h | 3 |
5 files changed, 10 insertions, 5 deletions
diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h index 30c267551386..66d5cb13fe0a 100644 --- a/src/southbridge/intel/bd82x6x/chip.h +++ b/src/southbridge/intel/bd82x6x/chip.h @@ -65,7 +65,7 @@ struct southbridge_intel_bd82x6x_config { int docking_supported; - uint8_t pcie_hotplug_map[8]; + bool pcie_hotplug_map[8]; /* Ports which can be routed to either EHCI or xHCI. */ uint32_t xhci_switchable_ports; diff --git a/src/southbridge/intel/common/pciehp.c b/src/southbridge/intel/common/pciehp.c index b5496192b09d..d5766d8f9073 100644 --- a/src/southbridge/intel/common/pciehp.c +++ b/src/southbridge/intel/common/pciehp.c @@ -4,10 +4,11 @@ #include <acpi/acpigen.h> #include <device/device.h> #include <device/pci.h> +#include <stdbool.h> #include "pciehp.h" -void intel_acpi_pcie_hotplug_generator(u8 *hotplug_map, int port_number) +void intel_acpi_pcie_hotplug_generator(bool *hotplug_map, int port_number) { int port; int have_hotplug = 0; diff --git a/src/southbridge/intel/common/pciehp.h b/src/southbridge/intel/common/pciehp.h index b4e65c4f46ad..beb210c7b037 100644 --- a/src/southbridge/intel/common/pciehp.h +++ b/src/southbridge/intel/common/pciehp.h @@ -1,9 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <stdbool.h> + #ifndef SOUTHBRIDGE_INTEL_COMMON_PCIEHP_H #define SOUTHBRIDGE_INTEL_COMMON_PCIEHP_H -void intel_acpi_pcie_hotplug_generator(u8 *hotplug_map, int port_number); +void intel_acpi_pcie_hotplug_generator(bool *hotplug_map, int port_number); void intel_acpi_pcie_hotplug_scan_slot(struct bus *bus); #endif diff --git a/src/southbridge/intel/i82801ix/chip.h b/src/southbridge/intel/i82801ix/chip.h index ec7b977081cf..d52a0c2006f5 100644 --- a/src/southbridge/intel/i82801ix/chip.h +++ b/src/southbridge/intel/i82801ix/chip.h @@ -3,6 +3,7 @@ #ifndef SOUTHBRIDGE_INTEL_I82801IX_CHIP_H #define SOUTHBRIDGE_INTEL_I82801IX_CHIP_H +#include <stdbool.h> #include <stdint.h> enum { @@ -73,7 +74,7 @@ struct southbridge_intel_i82801ix_config { uint8_t scale : 2; } pcie_power_limits[6]; - uint8_t pcie_hotplug_map[8]; + bool pcie_hotplug_map[8]; /* Additional LPC IO decode ranges */ uint32_t gen1_dec; diff --git a/src/southbridge/intel/i82801jx/chip.h b/src/southbridge/intel/i82801jx/chip.h index ae31d4f22437..f12a67e877c6 100644 --- a/src/southbridge/intel/i82801jx/chip.h +++ b/src/southbridge/intel/i82801jx/chip.h @@ -3,6 +3,7 @@ #ifndef SOUTHBRIDGE_INTEL_I82801JX_CHIP_H #define SOUTHBRIDGE_INTEL_I82801JX_CHIP_H +#include <stdbool.h> #include <stdint.h> enum { @@ -59,7 +60,7 @@ struct southbridge_intel_i82801jx_config { uint8_t scale : 2; } pcie_power_limits[6]; - uint8_t pcie_hotplug_map[8]; + bool pcie_hotplug_map[8]; /* Additional LPC IO decode ranges */ uint32_t gen1_dec; |