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| author | Jonathon Hall <jonathon.hall@puri.sm> | 2023-04-07 14:43:25 -0400 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-05-26 19:21:12 +0000 |
| commit | 247ec33eb995ebb10b423f86e965666e3a0ac8fa (patch) | |
| tree | 9f0030c2ac56b2bcb5c2d8e904225d54791e5dc5 /src/superio/common/chip.h | |
| parent | 1ff8768c8ccf22917f9dba4c780f3bdca4a72fde (diff) | |
| download | coreboot-247ec33eb995ebb10b423f86e965666e3a0ac8fa.tar.gz coreboot-247ec33eb995ebb10b423f86e965666e3a0ac8fa.tar.bz2 coreboot-247ec33eb995ebb10b423f86e965666e3a0ac8fa.zip | |
superio/common: Support more than one SuperIO in ACPI
The SuperIO ACPI name was hard-coded to "SIO0". Allow setting the name
in the device tree so more than one SuperIO can be named.
An upcoming board (purism/librem_l1um_v2) has two SuperIOs - one in the
AST2500 BMC, and a Nuvoton NCT6791D used for hardware monitor, POST
display, etc.
Many boards have references to SIO0 already, so the default name is
still the same for a single SuperIO.
Change-Id: Ibfa6ab7622749e6310ee91530bc3722e8e28d9bb
Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75089
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/superio/common/chip.h')
| -rw-r--r-- | src/superio/common/chip.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/superio/common/chip.h b/src/superio/common/chip.h index 737c90c5000f..2836a522f145 100644 --- a/src/superio/common/chip.h +++ b/src/superio/common/chip.h @@ -5,6 +5,9 @@ struct superio_common_config { /* FIXME: Add enter conf/exit conf codes here for SSDT generation */ + /* Rarely, boards may have more than one SuperIO. Give each SuperIO a + * unique name for ACPI. The default is 'SIO0'. */ + char acpi_name[5]; }; #endif /* __SUPERIO_COMMON_CHIP_H__ */ |