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| author | Angel Pons <th3fanbus@gmail.com> | 2020-06-05 18:20:39 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-06-08 12:05:02 +0000 |
| commit | e9b27e5527eb2ec1809801826da9632190ed8ffb (patch) | |
| tree | 1e6ae8cc17c60abdd0d42b33c2733096733aad37 /src/superio/nuvoton | |
| parent | 0d0b2f45f65afa6c845c4754de50d71f98a69394 (diff) | |
| download | coreboot-e9b27e5527eb2ec1809801826da9632190ed8ffb.tar.gz coreboot-e9b27e5527eb2ec1809801826da9632190ed8ffb.tar.bz2 coreboot-e9b27e5527eb2ec1809801826da9632190ed8ffb.zip | |
superio/nuvoton/nct6776: Reflow `pnp_dev_info` array
Each PnP device now fits in a single 96-character line.
With BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.
Change-Id: Ice65ce2504877c40962de7c26e01529d53d75c8e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42132
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Diffstat (limited to 'src/superio/nuvoton')
| -rw-r--r-- | src/superio/nuvoton/nct6776/superio.c | 63 |
1 files changed, 27 insertions, 36 deletions
diff --git a/src/superio/nuvoton/nct6776/superio.c b/src/superio/nuvoton/nct6776/superio.c index 6fcb93ec8f12..4197d54ad3e3 100644 --- a/src/superio/nuvoton/nct6776/superio.c +++ b/src/superio/nuvoton/nct6776/superio.c @@ -32,42 +32,33 @@ static struct device_operations ops = { }; static struct pnp_info pnp_dev_info[] = { - { NULL, NCT6776_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, - 0x0ff8, }, - { NULL, NCT6776_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, - 0x0ff8, }, - { NULL, NCT6776_SP1, PNP_IO0 | PNP_IRQ0, - 0x0ff8, }, - { NULL, NCT6776_SP2, PNP_IO0 | PNP_IRQ0, - 0x0ff8, }, - { NULL, NCT6776_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, - 0x0fff, 0x0fff, }, - { NULL, NCT6776_CIR, PNP_IO0 | PNP_IRQ0, - 0x0ff8, }, - { NULL, NCT6776_ACPI}, - { NULL, NCT6776_HWM_FPLED, PNP_IO0 | PNP_IO1 | PNP_IRQ0, - 0x0ffe, 0x0ffe, }, - { NULL, NCT6776_VID}, - { NULL, NCT6776_CIRWKUP, PNP_IO0 | PNP_IRQ0, - 0x0ff8, }, - { NULL, NCT6776_GPIO_PP_OD}, - { NULL, NCT6776_SVID}, - { NULL, NCT6776_DSLP}, - { NULL, NCT6776_GPIOA_LDN}, - { NULL, NCT6776_WDT1}, - { NULL, NCT6776_GPIOBASE, PNP_IO0, - 0x0ff8, }, - { NULL, NCT6776_GPIO0}, - { NULL, NCT6776_GPIO1}, - { NULL, NCT6776_GPIO2}, - { NULL, NCT6776_GPIO3}, - { NULL, NCT6776_GPIO4}, - { NULL, NCT6776_GPIO5}, - { NULL, NCT6776_GPIO6}, - { NULL, NCT6776_GPIO7}, - { NULL, NCT6776_GPIO8}, - { NULL, NCT6776_GPIO9}, - { NULL, NCT6776_GPIOA}, + { NULL, NCT6776_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x0ff8 }, + { NULL, NCT6776_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x0ff8 }, + { NULL, NCT6776_SP1, PNP_IO0 | PNP_IRQ0, 0x0ff8 }, + { NULL, NCT6776_SP2, PNP_IO0 | PNP_IRQ0, 0x0ff8 }, + { NULL, NCT6776_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, 0x0fff, 0x0fff }, + { NULL, NCT6776_CIR, PNP_IO0 | PNP_IRQ0, 0x0ff8 }, + { NULL, NCT6776_ACPI }, + { NULL, NCT6776_HWM_FPLED, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x0ffe, 0x0ffe }, + { NULL, NCT6776_VID }, + { NULL, NCT6776_CIRWKUP, PNP_IO0 | PNP_IRQ0, 0x0ff8 }, + { NULL, NCT6776_GPIO_PP_OD }, + { NULL, NCT6776_SVID }, + { NULL, NCT6776_DSLP }, + { NULL, NCT6776_GPIOA_LDN }, + { NULL, NCT6776_WDT1 }, + { NULL, NCT6776_GPIOBASE, PNP_IO0, 0x0ff8 }, + { NULL, NCT6776_GPIO0 }, + { NULL, NCT6776_GPIO1 }, + { NULL, NCT6776_GPIO2 }, + { NULL, NCT6776_GPIO3 }, + { NULL, NCT6776_GPIO4 }, + { NULL, NCT6776_GPIO5 }, + { NULL, NCT6776_GPIO6 }, + { NULL, NCT6776_GPIO7 }, + { NULL, NCT6776_GPIO8 }, + { NULL, NCT6776_GPIO9 }, + { NULL, NCT6776_GPIOA }, }; static void enable_dev(struct device *dev) |