vendorcode/amd/agesa/fam14: Remove dropped platform

This platform use the LEGACY_SMP_INIT which is to be deprecated after
release 4.18.

Change-Id: I9dd3ce763418ff767acd0c55be26a998df77081b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69124
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

27 files changed, 0 insertions, 6156 deletions

diff --git a/src/vendorcode/amd/agesa/f14/Config/OptionC6Install.h b/src/vendorcode/amd/agesa/f14/Config/OptionC6Install.h
deleted file mode 100644
index 14b15adb99f4..000000000000
--- a/src/vendorcode/amd/agesa/f14/Config/OptionC6Install.h
+++ /dev/null
@@ -1,108 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: C6 C-state
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Options
- * @e \$Revision: 37456 $   @e \$Date: 2010-09-04 04:17:05 +0800 (Sat, 04 Sep 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _OPTION_C6_STATE_INSTALL_H_
-#define _OPTION_C6_STATE_INSTALL_H_
-
-#include "cpuC6State.h"
-
-/*  This option is designed to be included into the platform solution install
- *  file. The platform solution install file will define the options status.
- *  Check to validate the definition
- */
-#define OPTION_C6_STATE_FEAT
-#define F14_C6_STATE_SUPPORT
-
-#if OPTION_C6_STATE == TRUE
-  #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE)
-
-    #ifdef OPTION_FAMILY14H
-      #if OPTION_FAMILY14H == TRUE
-        #if OPTION_FAMILY14H_ON == TRUE
-          extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureC6State;
-          #undef OPTION_C6_STATE_FEAT
-          #define OPTION_C6_STATE_FEAT &CpuFeatureC6State,
-          extern CONST C6_FAMILY_SERVICES ROMDATA F14C6Support;
-          #undef F14_C6_STATE_SUPPORT
-          #define F14_C6_STATE_SUPPORT {AMD_FAMILY_14_ON, &F14C6Support},
-
-          #if OPTION_EARLY_SAMPLES == TRUE
-            extern F_F14_ES_IS_C6_SUPPORTED F14IsC6DisabledEarlySample;
-            extern F_F14_ES_C6_INIT F14C6A0Workaround;
-
-            CONST F14_ES_C6_SUPPORT ROMDATA F14EarlySampleC6Support =
-            {
-              F14IsC6DisabledEarlySample,
-              F14C6A0Workaround
-            };
-          #else
-            CONST F14_ES_C6_SUPPORT ROMDATA F14EarlySampleC6Support =
-            {
-              (PF_F14_ES_IS_C6_SUPPORTED) CommonVoid,
-              (PF_F14_ES_C6_INIT) CommonVoid
-            };
-          #endif
-
-        #endif
-      #endif
-    #endif
-
-  #endif
-#endif
-
-CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA C6FamilyServiceArray[] =
-{
-  F14_C6_STATE_SUPPORT
-  {0, NULL}
-};
-
-CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA C6FamilyServiceTable =
-{
-  (sizeof (C6FamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
-  &C6FamilyServiceArray[0]
-};
-
-#endif  // _OPTION_C6_STATE_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f14/Config/OptionCpbInstall.h b/src/vendorcode/amd/agesa/f14/Config/OptionCpbInstall.h
deleted file mode 100644
index 4c9cf4c6b657..000000000000
--- a/src/vendorcode/amd/agesa/f14/Config/OptionCpbInstall.h
+++ /dev/null
@@ -1,91 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: Core Performance Boost
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Options
- * @e \$Revision: 34897 $   @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _OPTION_CPB_INSTALL_H_
-#define _OPTION_CPB_INSTALL_H_
-
-#include "cpuCpb.h"
-
-/*  This option is designed to be included into the platform solution install
- *  file. The platform solution install file will define the options status.
- *  Check to validate the definition
- */
-#define OPTION_CPB_FEAT
-#define F14_ON_CPB_SUPPORT
-
-#if OPTION_CPB == TRUE
-  #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)
-
-    // Family 14h
-    #ifdef OPTION_FAMILY14H
-      #if OPTION_FAMILY14H == TRUE
-        #if OPTION_FAMILY14H_ON == TRUE
-          extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCpb;
-          #undef OPTION_CPB_FEAT
-          #define OPTION_CPB_FEAT &CpuFeatureCpb,
-          extern CONST CPB_FAMILY_SERVICES ROMDATA F14OnCpbSupport;
-          #undef F14_ON_CPB_SUPPORT
-          #define F14_ON_CPB_SUPPORT {AMD_FAMILY_14_ON, &F14OnCpbSupport},
-        #endif
-      #endif
-    #endif
-
-  #endif
-#endif
-
-CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CpbFamilyServiceArray[] =
-{
-  F14_ON_CPB_SUPPORT
-  {0, NULL}
-};
-
-CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA CpbFamilyServiceTable =
-{
-  (sizeof (CpbFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
-  &CpbFamilyServiceArray[0]
-};
-
-#endif  // _OPTION_CPB_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f14/Config/OptionCpuCacheFlushOnHaltInstall.h b/src/vendorcode/amd/agesa/f14/Config/OptionCpuCacheFlushOnHaltInstall.h
deleted file mode 100644
index 42adc64cafaa..000000000000
--- a/src/vendorcode/amd/agesa/f14/Config/OptionCpuCacheFlushOnHaltInstall.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: CPU Cache Flush On Halt
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Options
- * @e \$Revision: 34897 $   @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _OPTION_CPU_CACHEFLUSHONHALT_INSTALL_H_
-#define _OPTION_CPU_CACHEFLUSHONHALT_INSTALL_H_
-
-#include "cpuPostInit.h"
-
-/*  This option is designed to be included into the platform solution install
- *  file. The platform solution install file will define the options status.
- *  Check to validate the definition
- */
-#define OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT
-
-
-CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CacheFlushOnHaltFamilyServiceArray[] =
-{
-  {0, NULL}
-};
-
-CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA CacheFlushOnHaltFamilyServiceTable =
-{
-  (sizeof (CacheFlushOnHaltFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
-  &CacheFlushOnHaltFamilyServiceArray[0]
-};
-
-#endif  // _OPTION_CPU_CACHEFLUSHONHALT_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f14/Config/OptionCpuCoreLevelingInstall.h b/src/vendorcode/amd/agesa/f14/Config/OptionCpuCoreLevelingInstall.h
deleted file mode 100644
index dcd5b9834491..000000000000
--- a/src/vendorcode/amd/agesa/f14/Config/OptionCpuCoreLevelingInstall.h
+++ /dev/null
@@ -1,68 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: CPU Core Leveling
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Options
- * @e \$Revision: 34897 $   @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _OPTION_CPU_CORELEVELING_INSTALL_H_
-#define _OPTION_CPU_CORELEVELING_INSTALL_H_
-
-
-/*  This option is designed to be included into the platform solution install
- *  file. The platform solution install file will define the options status.
- *  Check to validate the definition
- */
-#define OPTION_CPU_CORE_LEVELING_FEAT
-
-
-CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CoreLevelingFamilyServiceArray[] =
-{
-  {0, NULL}
-};
-CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA CoreLevelingFamilyServiceTable =
-{
-  (sizeof (CoreLevelingFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
-  &CoreLevelingFamilyServiceArray[0]
-};
-
-#endif  // _OPTION_CPU_CORELEVELING_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f14/Config/OptionCpuFamiliesInstall.h b/src/vendorcode/amd/agesa/f14/Config/OptionCpuFamiliesInstall.h
deleted file mode 100644
index 3fe6c022842f..000000000000
--- a/src/vendorcode/amd/agesa/f14/Config/OptionCpuFamiliesInstall.h
+++ /dev/null
@@ -1,357 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of all appropriate CPU family specific support.
- *
- * This file generates the defaults tables for all family specific
- * combinations.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Core
- * @e \$Revision: 37640 $   @e \$Date: 2010-09-08 23:01:59 +0800 (Wed, 08 Sep 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*  Default all CPU Specific Service members to off.  They
-    will be enabled as needed by cross referencing families
-    with entry points in the family / model install files.  */
-#define GET_PSTATE_POWER            FALSE
-#define GET_PSTATE_FREQ             FALSE
-#define DISABLE_PSTATE              FALSE
-#define TRANSITION_PSTATE           FALSE
-#define PROC_IDD_MAX                FALSE
-#define GET_TSC_RATE                FALSE
-#define PSTATE_TRANSITION_LATENCY   FALSE
-#define GET_PSTATE_REGISTER_INFO    FALSE
-#define GET_PSTATE_MAX_STATE        FALSE
-#define SET_PSTATE_LEVELING_REG     FALSE
-#define GET_NB_FREQ                 FALSE
-#define IS_NBCOF_INIT_NEEDED        FALSE
-#define AP_INITIAL_LAUNCH           FALSE
-#define GET_AP_MAILBOX_FROM_HW      FALSE
-#define SET_AP_CORE_NUMBER          FALSE
-#define GET_AP_CORE_NUMBER          FALSE
-#define TRANSFER_AP_CORE_NUMBER     FALSE
-#define ID_POSITION_INITIAL_APICID  FALSE
-#define SAVE_FEATURES               FALSE
-#define WRITE_FEATURES              FALSE
-#define SET_DOWN_CORE_REG           FALSE
-#define SET_WARM_RESET_FLAG         FALSE
-#define GET_WARM_RESET_FLAG         FALSE
-#define USES_REGISTER_TABLES        FALSE
-#define BASE_FAMILY_PCI             FALSE
-#define MODEL_SPECIFIC_PCI          FALSE
-#define BASE_FAMILY_MSR             FALSE
-#define MODEL_SPECIFIC_MSR          FALSE
-#define BRAND_STRING1               FALSE
-#define BRAND_STRING2               FALSE
-#define BASE_FAMILY_HT_PCI          FALSE
-#define MODEL_SPECIFIC_HT_PCI       FALSE
-#define BASE_FAMILY_WORKAROUNDS     FALSE
-#define GET_PATCHES                 FALSE
-#define GET_PATCHES_EQUIVALENCE_TABLE FALSE
-#define GET_CACHE_INFO              FALSE
-#define GET_SYSTEM_PM_TABLE         FALSE
-#define GET_WHEA_INIT               FALSE
-#define GET_CFOH_REG                FALSE
-#define GET_PLATFORM_TYPE_SPECIFIC_INFO FALSE
-#define IS_NB_PSTATE_ENABLED        FALSE
-
-/*
- * Pull in family specific services based on entry point
- */
-#if AGESA_ENTRY_INIT_RESET == TRUE
-  #undef ID_POSITION_INITIAL_APICID
-  #define ID_POSITION_INITIAL_APICID  TRUE
-  #undef GET_AP_MAILBOX_FROM_HW
-  #define GET_AP_MAILBOX_FROM_HW      TRUE
-  #undef SET_WARM_RESET_FLAG
-  #define SET_WARM_RESET_FLAG         TRUE
-  #undef GET_WARM_RESET_FLAG
-  #define GET_WARM_RESET_FLAG         TRUE
-  #undef GET_CACHE_INFO
-  #define GET_CACHE_INFO              TRUE
-  #undef GET_AP_CORE_NUMBER
-  #define GET_AP_CORE_NUMBER          TRUE
-  #undef TRANSFER_AP_CORE_NUMBER
-  #define TRANSFER_AP_CORE_NUMBER     TRUE
-#endif
-
-#if AGESA_ENTRY_INIT_EARLY == TRUE
-  #undef TRANSITION_PSTATE
-  #define TRANSITION_PSTATE           TRUE
-  #undef DISABLE_PSTATE
-  #define DISABLE_PSTATE              TRUE
-  #undef PROC_IDD_MAX
-  #define PROC_IDD_MAX                TRUE
-  #undef GET_TSC_RATE
-  #define GET_TSC_RATE                TRUE
-  #undef GET_NB_FREQ
-  #define GET_NB_FREQ                 TRUE
-  #undef IS_NBCOF_INIT_NEEDED
-  #define IS_NBCOF_INIT_NEEDED        TRUE
-  #undef AP_INITIAL_LAUNCH
-  #define AP_INITIAL_LAUNCH           TRUE
-  #undef GET_AP_MAILBOX_FROM_HW
-  #define GET_AP_MAILBOX_FROM_HW      TRUE
-  #undef SET_AP_CORE_NUMBER
-  #define SET_AP_CORE_NUMBER          TRUE
-  #undef GET_AP_CORE_NUMBER
-  #define GET_AP_CORE_NUMBER          TRUE
-  #undef TRANSFER_AP_CORE_NUMBER
-  #define TRANSFER_AP_CORE_NUMBER     TRUE
-  #undef ID_POSITION_INITIAL_APICID
-  #define ID_POSITION_INITIAL_APICID  TRUE
-  #undef SET_DOWN_CORE_REG
-  #define SET_DOWN_CORE_REG           TRUE
-  #undef SET_WARM_RESET_FLAG
-  #define SET_WARM_RESET_FLAG         TRUE
-  #undef GET_WARM_RESET_FLAG
-  #define GET_WARM_RESET_FLAG         TRUE
-  #undef USES_REGISTER_TABLES
-  #define USES_REGISTER_TABLES        TRUE
-  #undef BASE_FAMILY_PCI
-  #define BASE_FAMILY_PCI             TRUE
-  #undef MODEL_SPECIFIC_PCI
-  #define MODEL_SPECIFIC_PCI          TRUE
-  #undef BASE_FAMILY_MSR
-  #define BASE_FAMILY_MSR             TRUE
-  #undef MODEL_SPECIFIC_MSR
-  #define MODEL_SPECIFIC_MSR          TRUE
-  #undef BRAND_STRING1
-  #define BRAND_STRING1               TRUE
-  #undef BRAND_STRING2
-  #define BRAND_STRING2               TRUE
-  #undef BASE_FAMILY_HT_PCI
-  #define BASE_FAMILY_HT_PCI          TRUE
-  #undef MODEL_SPECIFIC_HT_PCI
-  #define MODEL_SPECIFIC_HT_PCI       TRUE
-  #undef BASE_FAMILY_WORKAROUNDS
-  #define BASE_FAMILY_WORKAROUNDS     TRUE
-  #undef GET_PATCHES
-  #define GET_PATCHES                 TRUE
-  #undef GET_PATCHES_EQUIVALENCE_TABLE
-  #define GET_PATCHES_EQUIVALENCE_TABLE TRUE
-  #undef GET_SYSTEM_PM_TABLE
-  #define GET_SYSTEM_PM_TABLE         TRUE
-  #undef GET_CACHE_INFO
-  #define GET_CACHE_INFO              TRUE
-  #undef GET_PLATFORM_TYPE_SPECIFIC_INFO
-  #define GET_PLATFORM_TYPE_SPECIFIC_INFO TRUE
-  #undef IS_NB_PSTATE_ENABLED
-  #define IS_NB_PSTATE_ENABLED        TRUE
-#endif
-
-#if AGESA_ENTRY_INIT_POST == TRUE
-  #undef ID_POSITION_INITIAL_APICID
-  #define ID_POSITION_INITIAL_APICID  TRUE
-  #undef GET_PSTATE_POWER
-  #define GET_PSTATE_POWER            TRUE
-  #undef GET_PSTATE_FREQ
-  #define GET_PSTATE_FREQ             TRUE
-  #undef TRANSITION_PSTATE
-  #define TRANSITION_PSTATE           TRUE
-  #undef PROC_IDD_MAX
-  #define PROC_IDD_MAX                TRUE
-  #undef GET_AP_CORE_NUMBER
-  #define GET_AP_CORE_NUMBER          TRUE
-  #undef GET_PSTATE_REGISTER_INFO
-  #define GET_PSTATE_REGISTER_INFO    TRUE
-  #undef GET_PSTATE_MAX_STATE
-  #define GET_PSTATE_MAX_STATE        TRUE
-  #undef SET_PSTATE_LEVELING_REG
-  #define SET_PSTATE_LEVELING_REG     TRUE
-  #undef SET_WARM_RESET_FLAG
-  #define SET_WARM_RESET_FLAG         TRUE
-  #undef GET_WARM_RESET_FLAG
-  #define GET_WARM_RESET_FLAG         TRUE
-  #undef SAVE_FEATURES
-  #define SAVE_FEATURES               TRUE
-  #undef WRITE_FEATURES
-  #define WRITE_FEATURES              TRUE
-  #undef GET_CFOH_REG
-  #define GET_CFOH_REG                TRUE
-  #undef IS_NB_PSTATE_ENABLED
-  #define IS_NB_PSTATE_ENABLED        TRUE
-#endif
-
-#if AGESA_ENTRY_INIT_ENV == TRUE
-#endif
-
-#if AGESA_ENTRY_INIT_MID == TRUE
-#endif
-
-#if AGESA_ENTRY_INIT_LATE == TRUE
-  #undef GET_AP_CORE_NUMBER
-  #define GET_AP_CORE_NUMBER          TRUE
-  #undef GET_PSTATE_FREQ
-  #define GET_PSTATE_FREQ             TRUE
-  #undef TRANSITION_PSTATE
-  #define TRANSITION_PSTATE           TRUE
-  #undef PSTATE_TRANSITION_LATENCY
-  #define PSTATE_TRANSITION_LATENCY   TRUE
-  #undef GET_WHEA_INIT
-  #define GET_WHEA_INIT               TRUE
-  #undef GET_PLATFORM_TYPE_SPECIFIC_INFO
-  #define GET_PLATFORM_TYPE_SPECIFIC_INFO TRUE
-  #undef GET_TSC_RATE
-  #define GET_TSC_RATE                TRUE
-  #undef BRAND_STRING1
-  #define BRAND_STRING1               TRUE
-  #undef BRAND_STRING2
-  #define BRAND_STRING2               TRUE
-#endif
-
-#if AGESA_ENTRY_INIT_S3SAVE == TRUE
-#endif
-
-#if AGESA_ENTRY_INIT_RESUME == TRUE
-  #undef GET_CFOH_REG
-  #define GET_CFOH_REG                TRUE
-#endif
-
-#if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE
-#endif
-
-#if AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE
-  #undef ID_POSITION_INITIAL_APICID
-  #define ID_POSITION_INITIAL_APICID  TRUE
-#endif
-
-/*
- * Initialize PCI MMIO mask to 0
- */
-#define FAMILY_MMIO_BASE_MASK (0ull)
-
-
-/*
- * Initialize all families to disabled
- */
-#define OPT_F14_TABLE
-
-#define OPT_F14_ID_TABLE
-
-
-/*
- * Install family specific support
- */
-
-#if (OPTION_FAMILY14H == TRUE)
-  #include  "OptionFamily14hInstall.h"
-#endif
-
-/*
- * Process PCI MMIO mask
- */
-
-// If size is 0, but base is not, break the build.
-#if (CFG_PCI_MMIO_BASE != 0) && (CFG_PCI_MMIO_SIZE == 0)
-  #error    BLDCFG: Invalid PCI MMIO size -- acceptable values are 1, 2, 4, 8, 16, 32, 64, 128, and 256
-#endif
-
-// If base is 0, but size is not, break the build.
-#if (CFG_PCI_MMIO_BASE == 0) && (CFG_PCI_MMIO_SIZE != 0)
-  #error    BLDCFG: Invalid PCI MMIO base -- must be 8MB or greater
-#endif
-
-#if (CFG_PCI_MMIO_BASE != 0) && (CFG_PCI_MMIO_SIZE != 0)
-  // Both are non-zero, begin further processing.
-
-  // Heap runs from 4MB to 8MB. Disallow any addresses below 8MB.
-  #if (CFG_PCI_MMIO_BASE < 0x800000)
-    #error    BLDCFG: Invalid PCI MMIO base -- must be 8MB or greater
-  #endif
-
-  // Break the build if the address is too high for the enabled families.
-  #if ((CFG_PCI_MMIO_BASE & FAMILY_MMIO_BASE_MASK) != 0)
-    #error       BLDCFG: Invalid PCI MMIO base address for the installed CPU families
-  #endif
-
-  // If the size parameter is not valid, break the build.
-  #if (CFG_PCI_MMIO_SIZE != 1) && (CFG_PCI_MMIO_SIZE != 2) && (CFG_PCI_MMIO_SIZE != 4) && (CFG_PCI_MMIO_SIZE != 8) && (CFG_PCI_MMIO_SIZE != 16)
-    #if (CFG_PCI_MMIO_SIZE != 32) && (CFG_PCI_MMIO_SIZE != 64) && (CFG_PCI_MMIO_SIZE != 128) && (CFG_PCI_MMIO_SIZE != 256)
-      #error      BLDCFG: Invalid PCI MMIO size -- acceptable values are 1, 2, 4, 8, 16, 32, 64, 128, and 256
-    #endif
-  #endif
-
-  #define PCI_MMIO_ALIGNMENT ((0x100000 * CFG_PCI_MMIO_SIZE) - 1)
-  // If the base is not aligned according to size, break the build.
-  #if ((CFG_PCI_MMIO_BASE & PCI_MMIO_ALIGNMENT) != 0)
-    #error      BLDCFG: Invalid PCI MMIO base -- must be properly aligned according to MMIO size
-  #endif
-  #undef PCI_MMIO_ALIGNMENT
-#endif
-
-/*
- * Process sockets / modules
- */
-#ifndef ADVCFG_PLATFORM_SOCKETS
-  #error BLDOPT Set Family supported sockets.
-#endif
-#ifndef ADVCFG_PLATFORM_MODULES
-  #error BLDOPT Set Family supported modules.
-#endif
-
-CONST OPTIONS_CONFIG_TOPOLOGY ROMDATA TopologyConfiguration =
-{
-  ADVCFG_PLATFORM_SOCKETS,
-  ADVCFG_PLATFORM_MODULES
-};
-
-/*
- * Instantiate global data needed for processor identification
- */
-CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CpuSupportedFamiliesArray[] =
-{
-  OPT_F14_TABLE
-};
-
-CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA CpuSupportedFamiliesTable =
-{
-  (sizeof (CpuSupportedFamiliesArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
-  &CpuSupportedFamiliesArray[0]
-};
-
-
-CONST CPU_LOGICAL_ID_FAMILY_XLAT ROMDATA CpuSupportedFamilyIdArray[] =
-{
-  OPT_F14_ID_TABLE
-};
-
-CONST CPU_FAMILY_ID_XLAT_TABLE ROMDATA CpuSupportedFamilyIdTable =
-{
-  (sizeof (CpuSupportedFamilyIdArray) / sizeof (CPU_LOGICAL_ID_FAMILY_XLAT)),
-  CpuSupportedFamilyIdArray
-};
diff --git a/src/vendorcode/amd/agesa/f14/Config/OptionCpuFeaturesInstall.h b/src/vendorcode/amd/agesa/f14/Config/OptionCpuFeaturesInstall.h
deleted file mode 100644
index c5519326e07d..000000000000
--- a/src/vendorcode/amd/agesa/f14/Config/OptionCpuFeaturesInstall.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of multiple CPU features.
- *
- * Aggregates enabled CPU features into a list for the dispatcher to process.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Options
- * @e \$Revision: 37157 $   @e \$Date: 2010-09-01 03:24:07 +0800 (Wed, 01 Sep 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _OPTION_CPU_FEATURES_INSTALL_H_
-#define _OPTION_CPU_FEATURES_INSTALL_H_
-
-#include "OptionHwC1eInstall.h"
-#include "OptionMsgBasedC1eInstall.h"
-#include "OptionSwC1eInstall.h"
-#include "OptionHtAssistInstall.h"
-#include "OptionCpuCoreLevelingInstall.h"
-#include "OptionIoCstateInstall.h"
-#include "OptionC6Install.h"
-#include "OptionCpbInstall.h"
-#include "OptionCpuCacheFlushOnHaltInstall.h"
-#include "OptionLowPwrPstateInstall.h"
-#include "OptionPreserveMailboxInstall.h"
-
-CONST CPU_FEATURE_DESCRIPTOR* ROMDATA CONST SupportedCpuFeatureList[] =
-{
-  OPTION_HW_C1E_FEAT
-  OPTION_MSG_BASED_C1E_FEAT
-  OPTION_SW_C1E_FEAT
-  OPTION_HT_ASSIST_FEAT
-  OPTION_CPU_CORE_LEVELING_FEAT
-  OPTION_IO_CSTATE_FEAT
-  OPTION_C6_STATE_FEAT
-  OPTION_CPB_FEAT
-  OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT
-  OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT_FEAT  // this function should be run before creating ACPI objects and after Pstate initialization
-  OPTION_PRESERVE_MAILBOX_FEAT
-  NULL
-};
-
-
-#endif  // _OPTION_CPU_FEATURES_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f14/Config/OptionDmiInstall.h b/src/vendorcode/amd/agesa/f14/Config/OptionDmiInstall.h
deleted file mode 100644
index 20600db71607..000000000000
--- a/src/vendorcode/amd/agesa/f14/Config/OptionDmiInstall.h
+++ /dev/null
@@ -1,129 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: DMI
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Options
- * @e \$Revision: 34897 $   @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _OPTION_DMI_INSTALL_H_
-#define _OPTION_DMI_INSTALL_H_
-
-#include "cpuLateInit.h"
-
-/*  This option is designed to be included into the platform solution install
- *  file. The platform solution install file will define the options status.
- *  Check to validate the definition
- */
-#if AGESA_ENTRY_INIT_LATE == TRUE
-  #ifndef OPTION_DMI
-    #error  BLDOPT: Option not defined: "OPTION_DMI"
-  #endif
-  #if OPTION_DMI == TRUE
-    OPTION_DMI_FEATURE          GetDmiInfoMain;
-    OPTION_DMI_RELEASE_BUFFER   ReleaseDmiBuffer;
-    #define USER_DMI_OPTION     &GetDmiInfoMain
-    #define USER_DMI_RELEASE_BUFFER &ReleaseDmiBuffer
-
-    // This additional check keeps AP launch routines from being unnecessarily included
-    // in single socket systems.
-    #if OPTION_MULTISOCKET == TRUE
-      #define CPU_DMI_AP_GET_TYPE4_TYPE7 {AP_LATE_TASK_GET_TYPE4_TYPE7, (IMAGE_ENTRY) GetType4Type7Info},
-    #else
-      #define CPU_DMI_AP_GET_TYPE4_TYPE7
-    #endif
-
-    // Family 14
-    #ifdef OPTION_FAMILY14H
-      #if OPTION_FAMILY14H == TRUE
-        extern PROC_FAMILY_TABLE ProcFamily14DmiTable;
-        #define FAM14_DMI_SUPPORT FAM14_ENABLED,
-        #define FAM14_DMI_TABLE &ProcFamily14DmiTable,
-      #else
-        #define FAM14_DMI_SUPPORT
-        #define FAM14_DMI_TABLE
-      #endif
-    #else
-      #define FAM14_DMI_SUPPORT
-      #define FAM14_DMI_TABLE
-    #endif
-
-  #else
-    OPTION_DMI_FEATURE          GetDmiInfoStub;
-    OPTION_DMI_RELEASE_BUFFER   ReleaseDmiBufferStub;
-    #define USER_DMI_OPTION     GetDmiInfoStub
-    #define USER_DMI_RELEASE_BUFFER ReleaseDmiBufferStub
-    #define FAM14_DMI_SUPPORT
-    #define FAM14_DMI_TABLE
-    #define CPU_DMI_AP_GET_TYPE4_TYPE7
-  #endif
-#else
-  OPTION_DMI_FEATURE          GetDmiInfoStub;
-  OPTION_DMI_RELEASE_BUFFER   ReleaseDmiBufferStub;
-  #define USER_DMI_OPTION     GetDmiInfoStub
-  #define USER_DMI_RELEASE_BUFFER ReleaseDmiBufferStub
-  #define FAM14_DMI_SUPPORT
-  #define FAM14_DMI_TABLE
-  #define CPU_DMI_AP_GET_TYPE4_TYPE7
-#endif
-
-/// DMI supported families enum
-typedef enum {
-  FAM14_DMI_SUPPORT                   ///< Conditionally define F14 support
-  NUM_DMI_FAMILIES                    ///< Number of installed families
-} AGESA_DMI_SUPPORTED_FAM;
-
-/*  Declare the Family List. An array of pointers to tables that each describe a family  */
-CONST PROC_FAMILY_TABLE ROMDATA *ProcTables[] = {
-  FAM14_DMI_TABLE
-  NULL
-};
-
-/*  Declare the instance of the DMI option configuration structure  */
-CONST OPTION_DMI_CONFIGURATION ROMDATA OptionDmiConfiguration = {
-  DMI_STRUCT_VERSION,
-  USER_DMI_OPTION,
-  USER_DMI_RELEASE_BUFFER,
-  NUM_DMI_FAMILIES,
-  (VOID *((*)[])) &ProcTables           // Compiler says array size must match struct decl
-};
-
-#endif  // _OPTION_DMI_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f14/Config/OptionFamily14hInstall.h b/src/vendorcode/amd/agesa/f14/Config/OptionFamily14hInstall.h
deleted file mode 100644
index 2750ac366f37..000000000000
--- a/src/vendorcode/amd/agesa/f14/Config/OptionFamily14hInstall.h
+++ /dev/null
@@ -1,669 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of family 14h support
- *
- * This file generates the default tables for family 14h processors.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Core
- * @e \$Revision: 37854 $   @e \$Date: 2010-09-14 06:35:39 +0800 (Tue, 14 Sep 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _OPTION_FAMILY_14H_INSTALL_H_
-#define _OPTION_FAMILY_14H_INSTALL_H_
-
-
-#include "OptionFamily14hEarlySample.h"
-
-/*
- * Common Family 14h routines
- */
-extern F_CPU_DISABLE_PSTATE F14DisablePstate;
-extern F_CPU_TRANSITION_PSTATE F14TransitionPstate;
-extern F_CPU_GET_TSC_RATE F14GetTscRate;
-extern F_CPU_GET_NB_FREQ F14GetCurrentNbFrequency;
-extern F_CPU_GET_NB_PSTATE_INFO F14GetNbPstateInfo;
-extern F_CPU_IS_NBCOF_INIT_NEEDED F14GetNbCofVidUpdate;
-extern F_CPU_AP_INITIAL_LAUNCH F14LaunchApCore;
-extern F_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE F14GetApMailboxFromHardware;
-extern F_CPU_GET_AP_CORE_NUMBER F14GetApCoreNumber;
-extern F_CORE_ID_POSITION_IN_INITIAL_APIC_ID F14CpuAmdCoreIdPositionInInitialApicId;
-extern F_CPU_SET_WARM_RESET_FLAG F14SetAgesaWarmResetFlag;
-extern F_CPU_GET_WARM_RESET_FLAG F14GetAgesaWarmResetFlag;
-extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF14BrandIdString1;
-extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF14BrandIdString2;
-extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF14CacheInfo;
-extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF14SysPmTable;
-extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF14WheaInitData;
-//extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetEmptyArray;
-extern F_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO F14GetPlatformTypeSpecificInfo;
-extern F_CPU_GET_IDD_MAX F14GetProcIddMax;
-extern CONST REGISTER_TABLE ROMDATA F14PciRegisterTable;
-extern CONST REGISTER_TABLE ROMDATA F14PerCorePciRegisterTable;
-extern CONST REGISTER_TABLE ROMDATA F14MsrRegisterTable;
-extern F_CPU_NUMBER_OF_BRANDSTRING_CORES F14GetNumberOfCoresForBrandstring;
-extern F_GET_EARLY_INIT_TABLE GetF14OnEarlyInitOnCoreTable;
-extern F_IS_NB_PSTATE_ENABLED F14IsNbPstateEnabled;
-#if OPTION_EARLY_SAMPLES == TRUE
-  extern CONST REGISTER_TABLE ROMDATA F14EarlySampleMsrRegisterTable;
-#endif
-
-
-/*
- * Install family 14h model 0 support
- */
-#ifdef OPTION_FAMILY14H_ON
-  #if OPTION_FAMILY14H_ON == TRUE
-    extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF14OnMicroCodePatchesStruct;
-    extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF14OnMicrocodeEquivalenceTable;
-    extern CONST REGISTER_TABLE ROMDATA F14OnPciRegisterTable;
-
-    #if USES_REGISTER_TABLES == TRUE
-      CONST REGISTER_TABLE ROMDATA * CONST F14OnRegisterTables[] =
-      {
-        #if BASE_FAMILY_PCI == TRUE
-          &F14PciRegisterTable,
-        #endif
-        #if BASE_FAMILY_PCI == TRUE
-          &F14PerCorePciRegisterTable,
-        #endif
-        #if BASE_FAMILY_MSR == TRUE
-          &F14MsrRegisterTable,
-          #if OPTION_EARLY_SAMPLES == TRUE
-            &F14EarlySampleMsrRegisterTable,
-          #endif
-        #endif
-        #if MODEL_SPECIFIC_PCI == TRUE
-          &F14OnPciRegisterTable,
-        #endif
-        // the end.
-        NULL
-      };
-    #endif
-
-    #if USES_REGISTER_TABLES == TRUE
-      CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F14OnTableEntryTypeDescriptors[] =
-      {
-        {MsrRegister, SetRegisterForMsrEntry},
-        {PciRegister, SetRegisterForPciEntry},
-        {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry},
-        // End
-        {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
-      };
-    #endif
-
-    CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF14OnServices =
-    {
-      0,
-      #if DISABLE_PSTATE == TRUE
-        F14DisablePstate,
-      #else
-        (PF_CPU_DISABLE_PSTATE) CommonAssert,
-      #endif
-      #if TRANSITION_PSTATE == TRUE
-        F14TransitionPstate,
-      #else
-        (PF_CPU_TRANSITION_PSTATE) CommonAssert,
-      #endif
-      #if PROC_IDD_MAX == TRUE
-        F14GetProcIddMax,
-      #else
-        (PF_CPU_GET_IDD_MAX) CommonAssert,
-      #endif
-      #if GET_TSC_RATE == TRUE
-        F14GetTscRate,
-      #else
-        (PF_CPU_GET_TSC_RATE) CommonAssert,
-      #endif
-      #if GET_NB_FREQ == TRUE
-        F14GetCurrentNbFrequency,
-      #else
-        (PF_CPU_GET_NB_FREQ) CommonAssert,
-      #endif
-      #if GET_NB_FREQ == TRUE
-        F14GetNbPstateInfo,
-      #else
-        (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert,
-      #endif
-      #if IS_NBCOF_INIT_NEEDED == TRUE
-        F14GetNbCofVidUpdate,
-      #else
-        (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
-      #endif
-      #if AP_INITIAL_LAUNCH == TRUE
-        F14LaunchApCore,
-      #else
-        (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
-      #endif
-      #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
-        F14GetNumberOfCoresForBrandstring,
-      #else
-        (PF_CPU_NUMBER_OF_BRANDSTRING_CORES) CommonAssert,
-      #endif
-      #if GET_AP_MAILBOX_FROM_HW == TRUE
-        F14GetApMailboxFromHardware,
-      #else
-        (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
-      #endif
-      #if SET_AP_CORE_NUMBER == TRUE
-        (PF_CPU_SET_AP_CORE_NUMBER) CommonVoid,
-      #else
-        (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
-      #endif
-      #if GET_AP_CORE_NUMBER == TRUE
-        F14GetApCoreNumber,
-      #else
-        (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
-      #endif
-      #if TRANSFER_AP_CORE_NUMBER == TRUE
-        (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonVoid,
-      #else
-        (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
-      #endif
-      #if ID_POSITION_INITIAL_APICID == TRUE
-        F14CpuAmdCoreIdPositionInInitialApicId,
-      #else
-        (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
-      #endif
-      #if SAVE_FEATURES == TRUE
-        (PF_CPU_SAVE_FEATURES) CommonVoid,
-      #else
-        (PF_CPU_SAVE_FEATURES) CommonAssert,
-      #endif
-      #if WRITE_FEATURES == TRUE
-        (PF_CPU_WRITE_FEATURES) CommonVoid,
-      #else
-        (PF_CPU_WRITE_FEATURES) CommonAssert,
-      #endif
-      #if SET_WARM_RESET_FLAG == TRUE
-        F14SetAgesaWarmResetFlag,
-      #else
-        (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
-      #endif
-      #if GET_WARM_RESET_FLAG == TRUE
-        F14GetAgesaWarmResetFlag,
-      #else
-        (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
-      #endif
-      #if BRAND_STRING1 == TRUE
-        GetF14BrandIdString1,
-      #else
-        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-      #endif
-      #if BRAND_STRING2 == TRUE
-        GetF14BrandIdString2,
-      #else
-        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-      #endif
-      #if GET_PATCHES == TRUE
-        GetF14OnMicroCodePatchesStruct,
-      #else
-        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-      #endif
-      #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
-        GetF14OnMicrocodeEquivalenceTable,
-      #else
-        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-      #endif
-      #if GET_CACHE_INFO == TRUE
-        GetF14CacheInfo,
-      #else
-        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-      #endif
-      #if GET_SYSTEM_PM_TABLE == TRUE
-        GetF14SysPmTable,
-      #else
-        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-      #endif
-      #if GET_WHEA_INIT == TRUE
-        GetF14WheaInitData,
-      #else
-        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-      #endif
-      #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
-        F14GetPlatformTypeSpecificInfo,
-      #else
-        (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
-      #endif
-      #if IS_NB_PSTATE_ENABLED == TRUE
-        F14IsNbPstateEnabled,
-      #else
-        (PF_IS_NB_PSTATE_ENABLED) CommonAssert,
-      #endif
-      #if (BASE_FAMILY_HT_PCI == TRUE)
-        (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
-      #else
-        (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
-      #endif
-      #if (BASE_FAMILY_HT_PCI == TRUE)
-        (PF_SET_HT_PHY_REGISTER) CommonVoid,
-      #else
-        (PF_SET_HT_PHY_REGISTER) CommonAssert,
-      #endif
-      #if BASE_FAMILY_PCI == TRUE
-        (PF_GET_NEXT_HT_LINK_FEATURES) CommonReturnFalse,
-      #else
-        (PF_GET_NEXT_HT_LINK_FEATURES) CommonReturnFalse,
-      #endif
-      #if USES_REGISTER_TABLES == TRUE
-        (REGISTER_TABLE **) F14OnRegisterTables,
-      #else
-        NULL,
-      #endif
-      #if USES_REGISTER_TABLES == TRUE
-        (TABLE_ENTRY_TYPE_DESCRIPTOR *) F14OnTableEntryTypeDescriptors,
-      #else
-        NULL,
-      #endif
-      #if MODEL_SPECIFIC_HT_PCI == TRUE
-        NULL,
-      #else
-        NULL,
-      #endif
-      NULL,
-      InitCacheDisabled,
-      #if AGESA_ENTRY_INIT_EARLY == TRUE
-        GetF14OnEarlyInitOnCoreTable
-      #else
-        (PF_GET_EARLY_INIT_TABLE) CommonVoid
-      #endif
-    };
-
-    #define ON_SOCKETS 1
-    #define ON_MODULES 1
-    #define ON_RECOVERY_SOCKETS 1
-    #define ON_RECOVERY_MODULES 1
-    extern F_CPU_GET_SUBFAMILY_ID_ARRAY GetF14OnLogicalIdAndRev;
-    #define OPT_F14_ON_ID (PF_CPU_GET_SUBFAMILY_ID_ARRAY) GetF14OnLogicalIdAndRev,
-    #ifndef ADVCFG_PLATFORM_SOCKETS
-      #define ADVCFG_PLATFORM_SOCKETS ON_SOCKETS
-    #else
-      #if ADVCFG_PLATFORM_SOCKETS < ON_SOCKETS
-        #undef ADVCFG_PLATFORM_SOCKETS
-        #define ADVCFG_PLATFORM_SOCKETS ON_SOCKETS
-      #endif
-    #endif
-    #ifndef ADVCFG_PLATFORM_MODULES
-      #define ADVCFG_PLATFORM_MODULES ON_MODULES
-    #else
-      #if ADVCFG_PLATFORM_MODULES < ON_MODULES
-        #undef ADVCFG_PLATFORM_MODULES
-        #define ADVCFG_PLATFORM_MODULES ON_MODULES
-      #endif
-    #endif
-
-    #if GET_PATCHES == TRUE
-      #define F14_ON_UCODE_0B
-      #define F14_ON_UCODE_1A
-      #define F14_ON_UCODE_29
-      #define F14_ON_UCODE_119
-
-      #if AGESA_ENTRY_INIT_EARLY == TRUE
-        #if OPTION_EARLY_SAMPLES == TRUE
-          extern  CONST MICROCODE_PATCHES ROMDATA CpuF14MicrocodePatch0500000B;
-          #undef F14_ON_UCODE_0B
-          #define F14_ON_UCODE_0B &CpuF14MicrocodePatch0500000B,
-
-          extern  CONST MICROCODE_PATCHES ROMDATA CpuF14MicrocodePatch0500001A;
-          #undef F14_ON_UCODE_1A
-          #define F14_ON_UCODE_1A &CpuF14MicrocodePatch0500001A,
-        #endif
-        extern  CONST MICROCODE_PATCHES ROMDATA CpuF14MicrocodePatch05000029;
-        #undef F14_ON_UCODE_29
-        #define F14_ON_UCODE_29 &CpuF14MicrocodePatch05000029,
-
-	extern  CONST MICROCODE_PATCHES ROMDATA CpuF14MicrocodePatch05000119;
-        #undef F14_ON_UCODE_119
-        #define F14_ON_UCODE_119 &CpuF14MicrocodePatch05000119,
-      #endif
-
-      CONST MICROCODE_PATCHES ROMDATA * CONST CpuF14OnMicroCodePatchArray[] =
-      {
-        F14_ON_UCODE_119
-        F14_ON_UCODE_29
-        F14_ON_UCODE_0B
-        F14_ON_UCODE_1A
-        NULL
-      };
-
-      CONST UINT8 ROMDATA CpuF14OnNumberOfMicrocodePatches = (UINT8) ((sizeof (CpuF14OnMicroCodePatchArray) / sizeof (CpuF14OnMicroCodePatchArray[0])) - 1);
-    #endif
-
-    #if OPTION_EARLY_SAMPLES == TRUE
-      extern F_F14_ES_GET_EARLY_INIT_TABLE GetF14OnEarlySampleEarlyInitTable;
-      extern F_F14_ES_NB_PSTATE_INIT F14NbPstateInitEarlySampleHook;
-      extern F_F14_ES_POWER_PLANE_INIT F14PowerPlaneInitEarlySampleHook;
-
-      CONST F14_ES_CORE_SUPPORT ROMDATA F14EarlySampleCoreSupport =
-      {
-        #if AGESA_ENTRY_INIT_EARLY == TRUE
-          GetF14OnEarlySampleEarlyInitTable,
-          F14PowerPlaneInitEarlySampleHook,
-        #else
-          (PF_F14_ES_GET_EARLY_INIT_TABLE) CommonAssert,
-          (PF_F14_ES_POWER_PLANE_INIT) CommonAssert,
-        #endif
-        #if (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE)
-          F14NbPstateInitEarlySampleHook
-        #else
-          (PF_F14_ES_NB_PSTATE_INIT) CommonAssert
-        #endif
-      };
-    #else
-      CONST F14_ES_CORE_SUPPORT ROMDATA F14EarlySampleCoreSupport =
-      {
-        #if AGESA_ENTRY_INIT_EARLY == TRUE
-          (PF_F14_ES_GET_EARLY_INIT_TABLE) CommonVoid,
-          (PF_F14_ES_POWER_PLANE_INIT) CommonVoid,
-        #else
-          (PF_F14_ES_GET_EARLY_INIT_TABLE) CommonAssert,
-          (PF_F14_ES_POWER_PLANE_INIT) CommonAssert,
-        #endif
-        #if (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE)
-          (PF_F14_ES_NB_PSTATE_INIT) CommonVoid
-        #else
-          (PF_F14_ES_NB_PSTATE_INIT) CommonAssert
-        #endif
-      };
-    #endif
-
-    #define OPT_F14_ON_CPU {AMD_FAMILY_14_ON, &cpuF14OnServices},
-  #else  //  OPTION_FAMILY14H_ON == TRUE
-    #define OPT_F14_ON_CPU
-    #define OPT_F14_ON_ID
-  #endif  //  OPTION_FAMILY14H_ON == TRUE
-#else  //  defined (OPTION_FAMILY14H_ON)
-  #define OPT_F14_ON_CPU
-  #define OPT_F14_ON_ID
-#endif  //  defined (OPTION_FAMILY14H_ON)
-
-/*
- * Install unknown family 14h support
- */
-
-#if USES_REGISTER_TABLES == TRUE
-  CONST REGISTER_TABLE ROMDATA * CONST F14UnknownRegisterTables[] =
-  {
-    #if BASE_FAMILY_PCI == TRUE
-      &F14PciRegisterTable,
-    #endif
-    #if BASE_FAMILY_PCI == TRUE
-      &F14PerCorePciRegisterTable,
-    #endif
-    #if BASE_FAMILY_MSR == TRUE
-      &F14MsrRegisterTable,
-    #endif
-    // the end.
-    NULL
-  };
-#endif
-
-#if USES_REGISTER_TABLES == TRUE
-  CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F14UnknownTableEntryTypeDescriptors[] =
-  {
-    {MsrRegister, SetRegisterForMsrEntry},
-    {PciRegister, SetRegisterForPciEntry},
-    {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry},
-    // End
-    {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
-  };
-#endif
-
-CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF14UnknownServices =
-{
-  0,
-  #if DISABLE_PSTATE == TRUE
-    F14DisablePstate,
-  #else
-    (PF_CPU_DISABLE_PSTATE) CommonAssert,
-  #endif
-  #if TRANSITION_PSTATE == TRUE
-    F14TransitionPstate,
-  #else
-    (PF_CPU_TRANSITION_PSTATE) CommonAssert,
-  #endif
-  #if PROC_IDD_MAX == TRUE
-    (PF_CPU_GET_IDD_MAX) F14GetProcIddMax,
-  #else
-    (PF_CPU_GET_IDD_MAX) CommonAssert,
-  #endif
-  #if GET_TSC_RATE == TRUE
-    F14GetTscRate,
-  #else
-    (PF_CPU_GET_TSC_RATE) CommonAssert,
-  #endif
-  #if GET_NB_FREQ == TRUE
-    F14GetCurrentNbFrequency,
-  #else
-    (PF_CPU_GET_NB_FREQ) CommonAssert,
-  #endif
-  #if GET_NB_FREQ == TRUE
-    F14GetNbPstateInfo,
-  #else
-    (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert,
-  #endif
-  #if IS_NBCOF_INIT_NEEDED == TRUE
-    F14GetNbCofVidUpdate,
-  #else
-    (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
-  #endif
-  #if AP_INITIAL_LAUNCH == TRUE
-    F14LaunchApCore,
-  #else
-    (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
-  #endif
-  #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
-    F14GetNumberOfCoresForBrandstring,
-  #else
-    (PF_CPU_NUMBER_OF_BRANDSTRING_CORES) CommonAssert,
-  #endif
-  #if GET_AP_MAILBOX_FROM_HW == TRUE
-    F14GetApMailboxFromHardware,
-  #else
-    (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
-  #endif
-  #if SET_AP_CORE_NUMBER == TRUE
-    (PF_CPU_SET_AP_CORE_NUMBER) CommonVoid,
-  #else
-    (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
-  #endif
-  #if GET_AP_CORE_NUMBER == TRUE
-    F14GetApCoreNumber,
-  #else
-    (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
-  #endif
-  #if TRANSFER_AP_CORE_NUMBER == TRUE
-    (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonVoid,
-  #else
-    (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
-  #endif
-  #if ID_POSITION_INITIAL_APICID == TRUE
-    F14CpuAmdCoreIdPositionInInitialApicId,
-  #else
-    (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
-  #endif
-  #if SAVE_FEATURES == TRUE
-    (PF_CPU_SAVE_FEATURES) CommonVoid,
-  #else
-    (PF_CPU_SAVE_FEATURES) CommonAssert,
-  #endif
-  #if WRITE_FEATURES == TRUE
-    (PF_CPU_WRITE_FEATURES) CommonVoid,
-  #else
-    (PF_CPU_WRITE_FEATURES) CommonAssert,
-  #endif
-  #if SET_WARM_RESET_FLAG == TRUE
-    F14SetAgesaWarmResetFlag,
-  #else
-    (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
-  #endif
-  #if GET_WARM_RESET_FLAG == TRUE
-    F14GetAgesaWarmResetFlag,
-  #else
-    (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
-  #endif
-  #if BRAND_STRING1 == TRUE
-    GetF14BrandIdString1,
-  #else
-    (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-  #endif
-  #if BRAND_STRING2 == TRUE
-    GetF14BrandIdString2,
-  #else
-    (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-  #endif
-  #if GET_PATCHES == TRUE
-    GetEmptyArray,
-  #else
-    (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-  #endif
-  #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
-    GetEmptyArray,
-  #else
-    (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-  #endif
-  #if GET_CACHE_INFO == TRUE
-    GetF14CacheInfo,
-  #else
-    (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-  #endif
-  #if GET_SYSTEM_PM_TABLE == TRUE
-    GetF14SysPmTable,
-  #else
-    (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-  #endif
-  #if GET_WHEA_INIT == TRUE
-    GetF14WheaInitData,
-  #else
-    (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
-  #endif
-  #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
-    F14GetPlatformTypeSpecificInfo,
-  #else
-    (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
-  #endif
-  #if IS_NB_PSTATE_ENABLED == TRUE
-    F14IsNbPstateEnabled,
-  #else
-    (PF_IS_NB_PSTATE_ENABLED) CommonAssert,
-  #endif
-  #if (BASE_FAMILY_HT_PCI == TRUE)
-    (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
-  #else
-    (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonVoid,
-  #endif
-  #if (BASE_FAMILY_HT_PCI == TRUE)
-    (PF_SET_HT_PHY_REGISTER) CommonVoid,
-  #else
-    (PF_SET_HT_PHY_REGISTER) CommonVoid,
-  #endif
-  #if BASE_FAMILY_PCI == TRUE
-    (PF_GET_NEXT_HT_LINK_FEATURES) CommonReturnFalse,
-  #else
-    (PF_GET_NEXT_HT_LINK_FEATURES) CommonReturnFalse,
-  #endif
-  #if USES_REGISTER_TABLES == TRUE
-    (REGISTER_TABLE **) F14UnknownRegisterTables,
-  #else
-    NULL,
-  #endif
-  #if USES_REGISTER_TABLES == TRUE
-    (TABLE_ENTRY_TYPE_DESCRIPTOR *) F14UnknownTableEntryTypeDescriptors,
-  #else
-    NULL,
-  #endif
-  #if MODEL_SPECIFIC_HT_PCI == TRUE
-    NULL,
-  #else
-    NULL,
-  #endif
-  NULL,
-  InitCacheDisabled,
-  #if AGESA_ENTRY_INIT_EARLY == TRUE
-    GetF14OnEarlyInitOnCoreTable
-  #else
-    (PF_GET_EARLY_INIT_TABLE) CommonVoid
-  #endif
-};
-
- // Family 14h maximum base address is 40 bits. Limit BLDCFG to 40 bits, if appropriate.
-#if (FAMILY_MMIO_BASE_MASK < 0xFFFFFF0000000000ull)
-  #undef  FAMILY_MMIO_BASE_MASK
-  #define FAMILY_MMIO_BASE_MASK (0xFFFFFF0000000000ull)
-#endif
-
-#undef OPT_F14_ID_TABLE
-#define OPT_F14_ID_TABLE {0x14, {AMD_FAMILY_14, AMD_F14_UNKNOWN}, F14LogicalIdTable, (sizeof (F14LogicalIdTable) / sizeof (F14LogicalIdTable[0]))},
-#define OPT_F14_UNKNOWN_CPU {AMD_FAMILY_14, &cpuF14UnknownServices},
-
-#undef OPT_F14_TABLE
-#define OPT_F14_TABLE   OPT_F14_ON_CPU  OPT_F14_UNKNOWN_CPU
-
-#if OPTION_FT1_SOCKET_SUPPORT == TRUE
-  extern CONST CPU_BRAND_TABLE ROMDATA F14OnBrandIdString1ArrayFt1;
-  extern CONST CPU_BRAND_TABLE ROMDATA F14OnBrandIdString2ArrayFt1;
-  #define F14_FT1_BRANDSTRING1 &F14OnBrandIdString1ArrayFt1,
-  #define F14_FT1_BRANDSTRING2 &F14OnBrandIdString2ArrayFt1,
-#else
-  #define F14_FT1_BRANDSTRING1
-  #define F14_FT1_BRANDSTRING2
-#endif
-
-#if BRAND_STRING1 == TRUE
-  CONST CPU_BRAND_TABLE ROMDATA * CONST F14BrandIdString1Tables[] =
-  {
-    F14_FT1_BRANDSTRING1
-  };
-
-  CONST UINT8 F14BrandIdString1TableCount = (sizeof (F14BrandIdString1Tables) / sizeof (F14BrandIdString1Tables[0]));
-#endif
-
-#if BRAND_STRING2 == TRUE
-  CONST CPU_BRAND_TABLE ROMDATA *CONST F14BrandIdString2Tables[] =
-  {
-    F14_FT1_BRANDSTRING2
-  };
-
-  CONST UINT8 F14BrandIdString2TableCount = (sizeof (F14BrandIdString2Tables) / sizeof (F14BrandIdString2Tables[0]));
-#endif
-
-CONST PF_CPU_GET_SUBFAMILY_ID_ARRAY ROMDATA F14LogicalIdTable[] =
-{
-  OPT_F14_ON_ID
-};
-
-#endif  // _OPTION_FAMILY_14H_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f14/Config/OptionGfxRecoveryInstall.h b/src/vendorcode/amd/agesa/f14/Config/OptionGfxRecoveryInstall.h
deleted file mode 100644
index c031f326c165..000000000000
--- a/src/vendorcode/amd/agesa/f14/Config/OptionGfxRecoveryInstall.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: GfxRecovery
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Options
- * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
- */
-/*****************************************************************************
- *
- * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ***************************************************************************/
-
-#ifndef _OPTION_GFX_RECOVERY_INSTALL_H_
-#define _OPTION_GFX_RECOVERY_INSTALL_H_
-
-/*  This option is designed to be included into the platform solution install
- *  file. The platform solution install file will define the options status.
- *  Check to validate the definition
- */
-
-
-#endif  // _OPTION_GFX_RECOVERY_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f14/Config/OptionGnbInstall.h b/src/vendorcode/amd/agesa/f14/Config/OptionGnbInstall.h
deleted file mode 100644
index f77c7baaa9b0..000000000000
--- a/src/vendorcode/amd/agesa/f14/Config/OptionGnbInstall.h
+++ /dev/null
@@ -1,490 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: GNB
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Options
- * @e \$Revision: 44325 $   @e \$Date: 2010-12-22 03:29:53 -0700 (Wed, 22 Dec 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _OPTION_GNB_INSTALL_H_
-#define _OPTION_GNB_INSTALL_H_
-
-#include "S3SaveState.h"
-/*  This option is designed to be included into the platform solution install
- *  file. The platform solution install file will define the options status.
- *  Check to validate the definition
- */
-
-#define GNB_TYPE_LN FALSE
-#define GNB_TYPE_ON OPTION_FAMILY14H
-#define GNB_TYPE_KR FALSE
-#define GNB_TYPE_TN FALSE
-
-#include "Gnb.h"
-#include "GnbPcie.h"
-
-#ifndef CFG_IGFX_AS_PCIE_EP
-  #define CFG_IGFX_AS_PCIE_EP     TRUE
-#endif
-
-#ifndef CFG_LCLK_DEEP_SLEEP_EN
-  #if (GNB_TYPE_ON == TRUE)
-    #define  CFG_LCLK_DEEP_SLEEP_EN   TRUE
-  #else
-    #define  CFG_LCLK_DEEP_SLEEP_EN   FALSE
-  #endif
-#endif
-
-#ifndef CFG_LCLK_DPM_EN
-  #if (GNB_TYPE_ON == TRUE)
-    #define CFG_LCLK_DPM_EN          TRUE
-  #else
-    #define CFG_LCLK_DPM_EN          FALSE
-  #endif
-#endif
-
-#ifndef CFG_GMC_POWER_GATE_STUTTER_ONLY
-  #define CFG_GMC_POWER_GATE_STUTTER_ONLY     FALSE
-#endif
-
-#ifndef CFG_SMU_SCLK_CLOCK_GATING_ENABLE
-  #if (GNB_TYPE_ON == TRUE)
-    #define  CFG_SMU_SCLK_CLOCK_GATING_ENABLE   TRUE
-  #else
-    #define CFG_SMU_SCLK_CLOCK_GATING_ENABLE   FALSE
-  #endif
-#endif
-
-#ifndef CFG_PCIE_ASPM_BLACK_LIST_ENABLE
-  #define CFG_PCIE_ASPM_BLACK_LIST_ENABLE     TRUE
-#endif
-
-#ifndef CFG_GNB_PCIE_LINK_RECEIVER_DETECTION_POOLING
-  #define CFG_GNB_PCIE_LINK_RECEIVER_DETECTION_POOLING  (60 * 1000)
-#endif
-
-#ifndef CFG_GNB_PCIE_LINK_L0_POOLING
-  #define CFG_GNB_PCIE_LINK_L0_POOLING                  (60 * 1000)
-#endif
-
-#ifndef CFG_GNB_PCIE_LINK_GPIO_RESET_ASSERT_TIME
-  #define CFG_GNB_PCIE_LINK_GPIO_RESET_ASSERT_TIME      (2 * 1000)
-#endif
-
-#ifndef CFG_GNB_PCIE_LINK_RESET_TO_TRAINING_TIME
-  #define CFG_GNB_PCIE_LINK_RESET_TO_TRAINING_TIME      (2 * 1000)
-#endif
-
-#ifdef BLDCFG_PCIE_TRAINING_ALGORITHM
-  #define CFG_GNB_PCIE_TRAINING_ALGORITHM               BLDCFG_PCIE_TRAINING_ALGORITHM
-#else
-  #define CFG_GNB_PCIE_TRAINING_ALGORITHM               PcieTrainingStandard
-#endif
-
-CONST GNB_BUILD_OPTIONS  GnbBuildOptions = {
-  CFG_IGFX_AS_PCIE_EP,
-  CFG_LCLK_DEEP_SLEEP_EN,
-  CFG_LCLK_DPM_EN,
-  CFG_GMC_POWER_GATE_STUTTER_ONLY,
-  CFG_SMU_SCLK_CLOCK_GATING_ENABLE,
-  CFG_PCIE_ASPM_BLACK_LIST_ENABLE,
-  CFG_GNB_PCIE_LINK_RECEIVER_DETECTION_POOLING,
-  CFG_GNB_PCIE_LINK_L0_POOLING,
-  CFG_GNB_PCIE_LINK_GPIO_RESET_ASSERT_TIME,
-  CFG_GNB_PCIE_LINK_RESET_TO_TRAINING_TIME,
-  CFG_GNB_PCIE_TRAINING_ALGORITHM
-};
-
-
-
-#if (AGESA_ENTRY_INIT_EARLY == TRUE)
-//---------------------------------------------------------------------------------------------------
-  #ifndef OPTION_NB_EARLY_INIT
-    #define OPTION_NB_EARLY_INIT TRUE
-  #endif
-  #if (OPTION_NB_EARLY_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
-    OPTION_GNB_FEATURE                                NbInitAtEarly;
-    #define OPTION_NBINITATEARLY_ENTRY                {AMD_FAMILY_LN | AMD_FAMILY_ON, NbInitAtEarly},
-  #else
-    #define OPTION_NBINITATEARLY_ENTRY
-  #endif
-//---------------------------------------------------------------------------------------------------
-// SMU init
-  #ifndef OPTION_SMU
-    #define OPTION_SMU  TRUE
-  #endif
-  #if (OPTION_SMU == TRUE) && (GNB_TYPE_LN == TRUE)
-    OPTION_GNB_FEATURE                                F12NbSmuInitFeature;
-    #define OPTION_F12NBSMUINITFEATURE_ENTRY          {AMD_FAMILY_LN, F12NbSmuInitFeature},
-  #else
-    #define OPTION_F12NBSMUINITFEATURE_ENTRY
-  #endif
-  #if (OPTION_SMU == TRUE) && (GNB_TYPE_ON == TRUE)
-    OPTION_GNB_FEATURE                                F14NbSmuInitFeature;
-    #define OPTION_F14NBSMUINITFEATURE_ENTRY          {AMD_FAMILY_ON, F14NbSmuInitFeature},
-  #else
-    #define OPTION_F14NBSMUINITFEATURE_ENTRY
-  #endif
-  #if (OPTION_SMU == TRUE) && (GNB_TYPE_KR == TRUE)
-    OPTION_GNB_FEATURE                                KRNbSmuInitFeature;
-    #define OPTION_KRNBSMUINITFEATURE_ENTRY          {AMD_FAMILY_KR, KRNbSmuInitFeature},
-  #else
-    #define OPTION_KRNBSMUINITFEATURE_ENTRY
-  #endif
-//---------------------------------------------------------------------------------------------------
-  #ifndef OPTION_PCIE_CONFIG_INIT
-    #define OPTION_PCIE_CONFIG_INIT TRUE
-  #endif
-  #if (OPTION_PCIE_CONFIG_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE  )
-    OPTION_GNB_FEATURE                                  PcieConfigurationInit;
-    #define OPTION_PCIECONFIGURATIONINIT_ENTRY          {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieConfigurationInit},
-  #else
-    #define OPTION_PCIECONFIGURATIONINIT_ENTRY
-  #endif
-//---------------------------------------------------------------------------------------------------
-  #ifndef OPTION_PCIE_EARLY_INIT
-    #define OPTION_PCIE_EARLY_INIT TRUE
-  #endif
-  #if (OPTION_PCIE_EARLY_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
-    OPTION_GNB_FEATURE                                   PcieInitAtEarly;
-    #define OPTION_PCIEINITATEARLY_ENTRY                 {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieInitAtEarly},
-  #else
-    #define  OPTION_PCIEINITATEARLY_ENTRY
-  #endif
-//---------------------------------------------------------------------------------------------------
-  CONST OPTION_GNB_CONFIGURATION  GnbEarlyFeatureTable[] = {
-    OPTION_NBINITATEARLY_ENTRY
-    OPTION_F12NBSMUINITFEATURE_ENTRY
-    OPTION_F14NBSMUINITFEATURE_ENTRY
-    OPTION_KRNBSMUINITFEATURE_ENTRY
-    OPTION_PCIECONFIGURATIONINIT_ENTRY
-    OPTION_PCIEINITATEARLY_ENTRY
-    {0, NULL}
-  };
-
-#endif
-
-#if (AGESA_ENTRY_INIT_POST == TRUE)
-//---------------------------------------------------------------------------------------------------
-  #ifndef OPTION_GFX_CONFIG_POST_INIT
-    #define OPTION_GFX_CONFIG_POST_INIT TRUE
-  #endif
-  #if (OPTION_GFX_CONFIG_POST_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE  )
-    OPTION_GNB_FEATURE                                   GfxConfigPostInterface;
-    #define OPTION_GFXCONFIGPOSTINTERFACE_ENTRY          {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxConfigPostInterface},
-  #else
-    #define  OPTION_GFXCONFIGPOSTINTERFACE_ENTRY
-  #endif
-//---------------------------------------------------------------------------------------------------
-  #ifndef OPTION_GFX_POST_INIT
-    #define OPTION_GFX_POST_INIT TRUE
-  #endif
-  #if (OPTION_GFX_POST_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
-    OPTION_GNB_FEATURE                                   GfxInitAtPost;
-    #define OPTION_GFXINITATPOST_ENTRY                   {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxInitAtPost},
-  #else
-   #define  OPTION_GFXINITATPOST_ENTRY
-  #endif
-//---------------------------------------------------------------------------------------------------
-  #ifndef OPTION_NB_POST_INIT
-    #define OPTION_NB_POST_INIT TRUE
-  #endif
-  #if (OPTION_NB_POST_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
-    OPTION_GNB_FEATURE                                  NbInitAtPost;
-    #define OPTION_NBINITATPOST_ENTRY                   {AMD_FAMILY_LN | AMD_FAMILY_ON, NbInitAtPost},
-  #else
-    #define OPTION_NBINITATPOST_ENTRY
-  #endif
-//---------------------------------------------------------------------------------------------------
-  #ifndef OPTION_PCIE_POST_EALRY_INIT
-    #define OPTION_PCIE_POST_EALRY_INIT TRUE
-  #endif
-  #if (OPTION_PCIE_POST_EALRY_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
-    OPTION_GNB_FEATURE                                  PcieInitAtPostEarly;
-    #define OPTION_PCIEINITATPOSTEARLY_ENTRY            {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieInitAtPostEarly},
-  #else
-    #define OPTION_PCIEINITATPOSTEARLY_ENTRY
-  #endif
-//---------------------------------------------------------------------------------------------------
-  #ifndef OPTION_PCIE_POST_INIT
-    #define OPTION_PCIE_POST_INIT TRUE
-  #endif
-  #if (OPTION_PCIE_POST_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
-    OPTION_GNB_FEATURE                                  PcieInitAtPost;
-    #define OPTION_PCIEINITATPOST_ENTRY                 {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieInitAtPost},
-  #else
-    #define OPTION_PCIEINITATPOST_ENTRY
-  #endif
-//---------------------------------------------------------------------------------------------------
-  CONST OPTION_GNB_CONFIGURATION  GnbPostFeatureTable[] = {
-    OPTION_PCIEINITATPOSTEARLY_ENTRY
-    OPTION_GFXCONFIGPOSTINTERFACE_ENTRY
-    OPTION_GFXINITATPOST_ENTRY
-    {0, NULL}
-  };
-
-  CONST OPTION_GNB_CONFIGURATION  GnbPostAfterDramFeatureTable[] = {
-    OPTION_NBINITATPOST_ENTRY
-    OPTION_PCIEINITATPOST_ENTRY
-    {0, NULL}
-  };
-#endif
-
-#if (AGESA_ENTRY_INIT_ENV == TRUE)
-//---------------------------------------------------------------------------------------------------
-  #ifndef OPTION_FUSE_TABLE_INIT
-    #define OPTION_FUSE_TABLE_INIT TRUE
-  #endif
-  #if (OPTION_FUSE_TABLE_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
-    OPTION_GNB_FEATURE                                  NbFuseTableFeature;
-    #define OPTION_NBFUSETABLEFEATURE_ENTRY             {AMD_FAMILY_LN | AMD_FAMILY_ON, NbFuseTableFeature},
-  #else
-    #define OPTION_NBFUSETABLEFEATURE_ENTRY
-  #endif
-//---------------------------------------------------------------------------------------------------
-  #ifndef OPTION_NB_ENV_INIT
-    #define OPTION_NB_ENV_INIT TRUE
-  #endif
-  #if (OPTION_NB_ENV_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
-    OPTION_GNB_FEATURE                                  NbInitAtEnv;
-    #define OPTION_NBINITATENVT_ENTRY                   {AMD_FAMILY_LN | AMD_FAMILY_ON, NbInitAtEnv},
-  #else
-    #define OPTION_NBINITATENVT_ENTRY
-  #endif
-//---------------------------------------------------------------------------------------------------
-  #ifndef OPTION_GFX_CONFIG_ENV_INIT
-    #define OPTION_GFX_CONFIG_ENV_INIT TRUE
-  #endif
-  #if (OPTION_GFX_CONFIG_ENV_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE  )
-    OPTION_GNB_FEATURE                                   GfxConfigEnvInterface;
-    #define OPTION_GFXCONFIGENVINTERFACE_ENTRY           {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxConfigEnvInterface},
-  #else
-    #define  OPTION_GFXCONFIGENVINTERFACE_ENTRY
-  #endif
-
-//---------------------------------------------------------------------------------------------------
-  #ifndef OPTION_GFX_ENV_INIT
-    #define OPTION_GFX_ENV_INIT TRUE
-  #endif
-  #if (OPTION_GFX_ENV_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
-    OPTION_GNB_FEATURE                                  GfxInitAtEnvPost;
-    #define OPTION_GFXINITATENVPOST_ENTRY               {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxInitAtEnvPost},
-  #else
-    #define OPTION_GFXINITATENVPOST_ENTRY
-  #endif
-//---------------------------------------------------------------------------------------------------
-  #ifndef OPTION_POWER_GATE
-    #define OPTION_POWER_GATE TRUE
-  #endif
-  #if (OPTION_POWER_GATE == TRUE) && (GNB_TYPE_LN == TRUE)
-    OPTION_GNB_FEATURE                                  F12NbPowerGateFeature;
-    #define OPTION_F12NBPOWERGATEFEATURE_ENTRY          {AMD_FAMILY_LN, F12NbPowerGateFeature},
-  #else
-    #define OPTION_F12NBPOWERGATEFEATURE_ENTRY
-  #endif
-  #if (OPTION_POWER_GATE == TRUE) && (GNB_TYPE_ON == TRUE)
-    OPTION_GNB_FEATURE                                  F14NbPowerGateFeature;
-    #define OPTION_F14NBPOWERGATEFEATURE_ENTRY          {AMD_FAMILY_ON, F14NbPowerGateFeature},
-  #else
-    #define OPTION_F14NBPOWERGATEFEATURE_ENTRY
-  #endif
-  #if (OPTION_POWER_GATE == TRUE) && (GNB_TYPE_KR == TRUE)
-    OPTION_GNB_FEATURE                                  KRNbPowerGateFeature;
-    #define OPTION_KRNBPOWERGATEFEATURE_ENTRY           {AMD_FAMILY_KR, KRNbPowerGateFeature},
-  #else
-    #define OPTION_KRNBPOWERGATEFEATURE_ENTRY
-  #endif
-//---------------------------------------------------------------------------------------------------
-  #ifndef OPTION_PCIE_ENV_INIT
-    #define OPTION_PCIE_ENV_INIT TRUE
-  #endif
-  #if (OPTION_PCIE_ENV_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
-    OPTION_GNB_FEATURE                                  PcieInitAtEnv;
-    #define OPTION_PCIEINITATENV_ENTRY                  {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieInitAtEnv},
-  #else
-    #define OPTION_PCIEINITATENV_ENTRY
-  #endif
-//---------------------------------------------------------------------------------------------------
-
-  CONST OPTION_GNB_CONFIGURATION  GnbEnvFeatureTable[] = {
-    OPTION_NBFUSETABLEFEATURE_ENTRY
-    OPTION_NBINITATENVT_ENTRY
-    OPTION_PCIEINITATENV_ENTRY
-    OPTION_GFXCONFIGENVINTERFACE_ENTRY
-    OPTION_GFXINITATENVPOST_ENTRY
-    OPTION_F12NBPOWERGATEFEATURE_ENTRY
-    OPTION_F14NBPOWERGATEFEATURE_ENTRY
-    OPTION_KRNBPOWERGATEFEATURE_ENTRY
-    {0, NULL}
-  };
-#endif
-
-#if (AGESA_ENTRY_INIT_MID == TRUE)
-//---------------------------------------------------------------------------------------------------
-  #ifndef OPTOIN_GNB_CABLESAFE
-    #define OPTOIN_GNB_CABLESAFE TRUE
-  #endif
-  #if (OPTOIN_GNB_CABLESAFE == TRUE) && (GNB_TYPE_LN == TRUE)
-    OPTION_GNB_FEATURE                                  GnbCableSafeEntry;
-    #define OPTION_GNBCABLESAFEENTRY_ENTRY              {AMD_FAMILY_LN, GnbCableSafeEntry},
-  #else
-    #define OPTION_GNBCABLESAFEENTRY_ENTRY
-  #endif
-//---------------------------------------------------------------------------------------------------
-  #ifndef OPTOIN_NB_LCLK_NCLK_RATIO
-    #define OPTOIN_NB_LCLK_NCLK_RATIO TRUE
-  #endif
-  #if (OPTOIN_NB_LCLK_NCLK_RATIO == TRUE) && (GNB_TYPE_ON == TRUE)
-    OPTION_GNB_FEATURE                                  F14NbLclkNclkRatioFeature;
-    #define OPTION_F14NBLCLKNCLKRATIOFEATURE_ENTRY      {AMD_FAMILY_ON, F14NbLclkNclkRatioFeature},
-  #else
-    #define OPTION_F14NBLCLKNCLKRATIOFEATURE_ENTRY
-  #endif
-  #if (OPTOIN_NB_LCLK_NCLK_RATIO == TRUE) && (GNB_TYPE_KR == TRUE)
-    OPTION_GNB_FEATURE                                  KRNbLclkNclkRatioFeature;
-    #define OPTION_KRNBLCLKNCLKRATIOFEATURE_ENTRY       {AMD_FAMILY_KR, KRNbLclkNclkRatioFeature},
-  #else
-    #define OPTION_KRNBLCLKNCLKRATIOFEATURE_ENTRY
-  #endif
-//---------------------------------------------------------------------------------------------------
-  #ifndef OPTION_NB_LCLK_DPM_INIT
-    #define OPTION_NB_LCLK_DPM_INIT TRUE
-  #endif
-  #if (OPTION_NB_LCLK_DPM_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
-    OPTION_GNB_FEATURE                                  NbLclkDpmFeature;
-    #define OPTION_NBLCLKDPMFEATURE_ENTRY               {AMD_FAMILY_LN | AMD_FAMILY_ON, NbLclkDpmFeature},
-  #else
-    #define OPTION_NBLCLKDPMFEATURE_ENTRY
-  #endif
-//---------------------------------------------------------------------------------------------------
-  #ifndef OPTION_PCIE_POWER_GATE
-    #define OPTION_PCIE_POWER_GATE TRUE
-  #endif
-  #if (OPTION_PCIE_POWER_GATE == TRUE) && (GNB_TYPE_LN == TRUE)
-    OPTION_GNB_FEATURE                                  PciePowerGateFeature;
-    #define OPTION_PCIEPOWERGATEFEATURE_ENTRY           {AMD_FAMILY_LN, PciePowerGateFeature},
-  #else
-    #define OPTION_PCIEPOWERGATEFEATURE_ENTRY
-  #endif
-//---------------------------------------------------------------------------------------------------
-  #ifndef OPTION_GFX_MID_INIT
-    #define OPTION_GFX_MID_INIT TRUE
-  #endif
-  #if (OPTION_GFX_MID_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
-    OPTION_GNB_FEATURE                                  GfxInitAtMidPost;
-    #define OPTION_GFXINITATMIDPOST_ENTRY               {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxInitAtMidPost},
-  #else
-    #define OPTION_GFXINITATMIDPOST_ENTRY
-  #endif
-//---------------------------------------------------------------------------------------------------
-  #ifndef OPTION_GFX_INTEGRATED_TABLE_INIT
-    #define OPTION_GFX_INTEGRATED_TABLE_INIT TRUE
-  #endif
-  #if (OPTION_GFX_INTEGRATED_TABLE_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
-    OPTION_GNB_FEATURE                                 GfxIntegratedInfoTableEntry;
-    #define OPTION_GFXINTEGRATEDINFOTABLE_ENTRY        {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxIntegratedInfoTableEntry},
-  #else
-    #define OPTION_GFXINTEGRATEDINFOTABLE_ENTRY
-  #endif
-//---------------------------------------------------------------------------------------------------
-  #ifndef OPTION_PCIe_MID_INIT
-    #define OPTION_PCIe_MID_INIT TRUE
-  #endif
-  #if (OPTION_PCIe_MID_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
-    OPTION_GNB_FEATURE                                  PcieInitAtMid;
-    #define OPTION_PCIEINITATMID_ENTRY                  {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieInitAtMid},
-  #else
-    #define OPTION_PCIEINITATMID_ENTRY
-  #endif
-//---------------------------------------------------------------------------------------------------
-  #ifndef OPTION_NB_MID_INIT
-    #define OPTION_NB_MID_INIT TRUE
-  #endif
-  #if (OPTION_NB_MID_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
-    OPTION_GNB_FEATURE                                  NbInitAtLatePost;
-    #define OPTION_NBINITATLATEPOST_ENTRY               {AMD_FAMILY_LN | AMD_FAMILY_ON, NbInitAtLatePost},
-  #else
-    #define OPTION_NBINITATLATEPOST_ENTRY
-  #endif
-//---------------------------------------------------------------------------------------------------
-  CONST OPTION_GNB_CONFIGURATION  GnbMidFeatureTable[] = {
-    OPTION_GFXINITATMIDPOST_ENTRY
-    OPTION_GFXINTEGRATEDINFOTABLE_ENTRY
-    OPTION_GNBCABLESAFEENTRY_ENTRY
-    OPTION_PCIEINITATMID_ENTRY
-    OPTION_NBINITATLATEPOST_ENTRY
-    OPTION_F14NBLCLKNCLKRATIOFEATURE_ENTRY
-    OPTION_KRNBLCLKNCLKRATIOFEATURE_ENTRY
-    OPTION_NBLCLKDPMFEATURE_ENTRY
-    OPTION_PCIEPOWERGATEFEATURE_ENTRY
-    {0, NULL}
-  };
-#endif
-
-#if (AGESA_ENTRY_INIT_LATE == TRUE)
-//---------------------------------------------------------------------------------------------------
-  #ifndef OPTION_ALIB
-    #define OPTION_ALIB FALSE
-  #endif
-  #if (OPTION_ALIB == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE  )
-    OPTION_GNB_FEATURE                                  PcieAlibFeature;
-    #define OPTION_PCIEALIBFEATURE_ENTRY                {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieAlibFeature},
-  #else
-    #define OPTION_PCIEALIBFEATURE_ENTRY
-  #endif
-//---------------------------------------------------------------------------------------------------
-  CONST OPTION_GNB_CONFIGURATION  GnbLateFeatureTable[] = {
-    OPTION_PCIEALIBFEATURE_ENTRY
-    {0, NULL}
-  };
-#endif
-
-#if  (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
-  S3_DISPATCH_FUNCTION  NbSmuServiceRequestS3Script;
-  S3_DISPATCH_FUNCTION  PcieLateRestoreS3Script;
-  S3_DISPATCH_FUNCTION  NbSmuIndirectWriteS3Script;
-  #define GNB_S3_DISPATCH_FUNCTION_TABLE \
-  {S3DispatchGnbSmuIndirectWrite, NbSmuIndirectWriteS3Script}, \
-  {S3DispatchGnbSmuServiceRequest, NbSmuServiceRequestS3Script}, \
-  {S3DispatchGnbPcieLateRestore, PcieLateRestoreS3Script},
-#endif
-
-#endif  // _OPTION_GNB_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f14/Config/OptionHtAssistInstall.h b/src/vendorcode/amd/agesa/f14/Config/OptionHtAssistInstall.h
deleted file mode 100644
index 4536b478c5c6..000000000000
--- a/src/vendorcode/amd/agesa/f14/Config/OptionHtAssistInstall.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: HT Assist
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Options
- * @e \$Revision: 34897 $   @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _OPTION_HT_ASSIST_INSTALL_H_
-#define _OPTION_HT_ASSIST_INSTALL_H_
-
-#include "cpuHtAssist.h"
-
-/*  This option is designed to be included into the platform solution install
- *  file. The platform solution install file will define the options status.
- *  Check to validate the definition
- */
-#define OPTION_HT_ASSIST_FEAT
-#define HT_ASSIST_AP_DISABLE_CACHE
-#define HT_ASSIST_AP_ENABLE_CACHE
-
-#if (OPTION_HT_ASSIST == TRUE || OPTION_ATM_MODE == TRUE)
-  #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_MID == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)
-
-    CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA HtAssistFamilyServiceArray[] =
-    {
-      {0, NULL}
-    };
-    CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA HtAssistFamilyServiceTable =
-    {
-      (sizeof (HtAssistFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
-      &HtAssistFamilyServiceArray[0]
-    };
-
-    #undef HT_ASSIST_AP_DISABLE_CACHE
-    #define HT_ASSIST_AP_DISABLE_CACHE {AP_LATE_TASK_DISABLE_CACHE, (IMAGE_ENTRY) DisableAllCaches},
-    #undef HT_ASSIST_AP_ENABLE_CACHE
-    #define HT_ASSIST_AP_ENABLE_CACHE {AP_LATE_TASK_ENABLE_CACHE, (IMAGE_ENTRY) EnableAllCaches},
-  #endif
-#endif
-
-#endif  // _OPTION_HT_ASSIST_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f14/Config/OptionHtInstall.h b/src/vendorcode/amd/agesa/f14/Config/OptionHtInstall.h
deleted file mode 100644
index f561b7387c33..000000000000
--- a/src/vendorcode/amd/agesa/f14/Config/OptionHtInstall.h
+++ /dev/null
@@ -1,248 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: Ht
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Options
- * @e \$Revision: 34897 $   @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _OPTION_HT_INSTALL_H_
-#define _OPTION_HT_INSTALL_H_
-
-#include "Topology.h"
-#include "htFeat.h"
-#include "htInterface.h"
-#include "htNb.h"
-#include "htTopologies.h"
-/*
- * Advanced Option only, hardware socket naming is the preferred method.
- */
-#ifdef BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP
-  #define CFG_SYSTEM_PHYSICAL_SOCKET_MAP         (BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP)
-#else
-  #define CFG_SYSTEM_PHYSICAL_SOCKET_MAP         (NULL)
-#endif
-
-/*
- * OPTION_IS_RECOVERY_HT is true if Basic API is being used.
- */
-#ifndef OPTION_IS_RECOVERY_HT
-  #define OPTION_IS_RECOVERY_HT TRUE
-#endif
-
-/*  This option is designed to be included into the platform solution install
- *  file. The platform solution install file will define the options status.
- *  Check to validate the definition.
- */
-
-#ifndef OPTION_MULTISOCKET
-  #error  BLDOPT: Option not defined: "OPTION_MULTISOCKET"
-#endif
-
-/*
- * Based on user level options, set Ht internal options.
- * this will have to be changed to not set non-coherent only.
- */
-#define OPTION_HT_NON_COHERENT_ONLY FALSE
-
-/* Fusion Families do not need a non-coherent only option. */
-
-/*
- * Macros will generate the correct item reference based on options
- */
-#if AGESA_ENTRY_INIT_EARLY == TRUE
-  // Select the interface and features
-  #if OPTION_FAMILY14H == TRUE
-    #define INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES NULL
-    #define INTERNAL_HT_OPTION_FEATURES     &HtFeaturesNone
-    #define INTERNAL_HT_OPTION_INTERFACE    &HtInterfaceMapsOnly
-    #define INTERNAL_HT_OPTION_FAM14_NB     &HtFam14Nb,
-  #else
-    #define INTERNAL_HT_OPTION_FAM14_NB
-  #endif
-
-  #define INTERNAL_ONLY_NB_LIST_ITEM INTERNAL_ONLY_HT_OPTION_SUPPORTED_NBS,
-  #ifndef INTERNAL_ONLY_HT_OPTION_SUPPORTED_NBS
-    #undef INTERNAL_ONLY_NB_LIST_ITEM
-    #define INTERNAL_ONLY_NB_LIST_ITEM
-  #endif
-
-  /* Install the correct set of northbridge implementations. Each item provides its own comma, the last item
-   * is ok to have a comma because the final item (NULL) is added below.
-   */
-  #define INTERNAL_HT_OPTION_SUPPORTED_NBS \
-                                             INTERNAL_ONLY_NB_LIST_ITEM \
-                                             INTERNAL_HT_OPTION_FAM14_NB
-
-#else
-  // Not Init Early
-  #define INTERNAL_HT_OPTION_FEATURES     NULL
-  #define INTERNAL_HT_OPTION_INTERFACE    NULL
-  #define INTERNAL_HT_OPTION_SUPPORTED_NBS NULL
-  #define HT_OPTIONS_PLATFORM             NULL
-  #define INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES NULL
-#endif
-
-#ifdef AGESA_ENTRY_INIT_EARLY
-  #if AGESA_ENTRY_INIT_EARLY == TRUE
-
-    extern HT_FEATURES HtFeaturesDefault;
-    extern HT_FEATURES HtFeaturesNonCoherentOnly;
-    extern HT_FEATURES HtFeaturesNone;
-    extern HT_INTERFACE HtInterfaceDefault;
-    extern HT_INTERFACE HtInterfaceNonCoherentOnly;
-    extern HT_INTERFACE HtInterfaceMapsOnly;
-    extern HT_INTERFACE HtInterfaceNone;
-    extern NORTHBRIDGE HtFam10NbDefault;
-    extern NORTHBRIDGE HtFam10RevDNbDefault;
-    extern NORTHBRIDGE HtFam10NbNonCoherentOnly;
-    extern NORTHBRIDGE HtFam10RevDNbNonCoherentOnly;
-    extern NORTHBRIDGE HtFam12Nb;
-    extern NORTHBRIDGE HtFam14Nb;
-    extern NORTHBRIDGE HtFam10NbNone;
-    extern NORTHBRIDGE HtFam15NbDefault;
-    extern NORTHBRIDGE HtFam15NbNonCoherentOnly;
-
-    CONST VOID * CONST ROMDATA HtInstalledFamilyNorthbridgeList[] = {
-      INTERNAL_HT_OPTION_SUPPORTED_NBS
-      NULL
-    };
-
-    STATIC CONST AMD_HT_INTERFACE ROMDATA HtOptionsPlatform =
-    {
-      CFG_STARTING_BUSNUM, CFG_MAXIMUM_BUSNUM, CFG_ALLOCATED_BUSNUM,
-      (MANUAL_BUID_SWAP_LIST *)CFG_BUID_SWAP_LIST,
-      (DEVICE_CAP_OVERRIDE *)CFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST,
-      (CPU_TO_CPU_PCB_LIMITS *)CFG_HTFABRIC_LIMITS_LIST,
-      (IO_PCB_LIMITS *)CFG_HTCHAIN_LIMITS_LIST,
-      (OVERRIDE_BUS_NUMBERS *)CFG_BUS_NUMBERS_LIST,
-      (IGNORE_LINK *)CFG_IGNORE_LINK_LIST,
-      (SKIP_REGANG *)CFG_LINK_SKIP_REGANG_LIST,
-      (UINT8 **)CFG_ADDITIONAL_TOPOLOGIES_LIST,
-      (SYSTEM_PHYSICAL_SOCKET_MAP *)CFG_SYSTEM_PHYSICAL_SOCKET_MAP
-    };
-    #ifndef HT_OPTIONS_PLATFORM
-      #define HT_OPTIONS_PLATFORM &HtOptionsPlatform
-    #endif
-
-    /**
-     * A list of all the supported topologies.
-     *
-     */
-    #ifndef INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES
-      CONST UINT8 *CONST ROMDATA AmdTopolist[] =
-      {
-        amdHtTopologySingleNode,
-        amdHtTopologyDualNode,
-        amdHtTopologyThreeLine,
-        amdHtTopologyTriangle,
-        amdHtTopologyFourLine,
-        amdHtTopologyFourStar,
-        amdHtTopologyFourDegenerate,
-        amdHtTopologyFourSquare,
-        amdHtTopologyFourKite,
-        amdHtTopologyFourFully,
-        amdHtTopologyFiveFully,
-        amdHtTopologyFiveTwistedLadder,
-        amdHtTopologySixFully,
-        amdHtTopologySixDoubloonLower,
-        amdHtTopologySixDoubloonUpper,
-        amdHtTopologySixTwistedLadder,
-        amdHtTopologySevenFully,
-        amdHtTopologySevenTwistedLadder,
-        amdHtTopologyEightFully,
-        amdHtTopologyEightDoubloon,
-        amdHtTopologyEightTwistedLadder,
-        amdHtTopologyEightStraightLadder,
-        amdHtTopologySixTwinTriangles,
-        amdHtTopologyEightTwinFullyFourWays,
-        NULL
-      };
-      #define INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES AmdTopolist
-    #endif
-
-    /**
-     * Declare the instance of the Ht option configuration structure
-     */
-    CONST OPTION_HT_CONFIGURATION ROMDATA OptionHtConfiguration = {
-      OPTION_IS_RECOVERY_HT,
-      CFG_SET_HTCRC_SYNC_FLOOD,
-      CFG_USE_UNIT_ID_CLUMPING,
-      HT_OPTIONS_PLATFORM,
-      INTERNAL_HT_OPTION_INTERFACE,
-      INTERNAL_HT_OPTION_FEATURES,
-      &HtInstalledFamilyNorthbridgeList,
-      INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES
-    };
-
-  #endif
-#endif
-
-#ifndef OPTION_HT_INIIT_RESET_ENTRY
-
-  #define OPTION_HT_INIIT_RESET_ENTRY AmdHtInitReset
-
-  #if OPTION_FAMILY14H == TRUE
-    #undef OPTION_HT_INIIT_RESET_ENTRY
-    #undef OPTION_HT_INIIT_RESET_CONSTRUCTOR_ENTRY
-    #define OPTION_HT_INIIT_RESET_ENTRY NULL
-    #define OPTION_HT_INIIT_RESET_CONSTRUCTOR_ENTRY NULL
-  #endif
-
-#endif
-
-#ifdef AGESA_ENTRY_INIT_RESET
-  #if AGESA_ENTRY_INIT_RESET == TRUE
-
-    CONST AMD_HT_RESET_INTERFACE ROMDATA HtOptionResetDefaults = {
-      (MANUAL_BUID_SWAP_LIST *)CFG_BUID_SWAP_LIST,
-      0                                            // Unused by options
-    };
-
-    CONST OPTION_HT_INIT_RESET ROMDATA HtOptionInitReset = {
-      OPTION_HT_INIIT_RESET_ENTRY,
-      OPTION_HT_INIIT_RESET_CONSTRUCTOR_ENTRY
-    };
-  #endif
-
-#endif
-
-#endif  // _OPTION_HT_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f14/Config/OptionHwC1eInstall.h b/src/vendorcode/amd/agesa/f14/Config/OptionHwC1eInstall.h
deleted file mode 100644
index 52b15c7184f3..000000000000
--- a/src/vendorcode/amd/agesa/f14/Config/OptionHwC1eInstall.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: HW C1e
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Options
- * @e \$Revision: 34897 $   @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _OPTION_HW_C1E_INSTALL_H_
-#define _OPTION_HW_C1E_INSTALL_H_
-
-#include "cpuHwC1e.h"
-
-/*  This option is designed to be included into the platform solution install
- *  file. The platform solution install file will define the options status.
- *  Check to validate the definition
- */
-#define OPTION_HW_C1E_FEAT
-#if AGESA_ENTRY_INIT_EARLY == TRUE
-  CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA HwC1eFamilyServiceArray[] =
-  {
-    {0, NULL}
-  };
-  CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA HwC1eFamilyServiceTable =
-  {
-    (sizeof (HwC1eFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
-    &HwC1eFamilyServiceArray[0]
-  };
-#endif
-
-#endif  // _OPTION_HW_C1E_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f14/Config/OptionIdsInstall.h b/src/vendorcode/amd/agesa/f14/Config/OptionIdsInstall.h
deleted file mode 100644
index 9347eeb60d10..000000000000
--- a/src/vendorcode/amd/agesa/f14/Config/OptionIdsInstall.h
+++ /dev/null
@@ -1,281 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * IDS Option Install File
- *
- * This file generates the defaults tables for family 10h model 5 processors.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Core
- * @e \$Revision: 34897 $   @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-#ifndef _OPTION_IDS_INSTALL_H_
-#define _OPTION_IDS_INSTALL_H_
-#include "Ids.h"
-#include "IdsHt.h"
-#include "IdsLib.h"
-#ifdef __IDS_EXTENDED__
-  #include OPTION_IDS_EXT_INSTALL_FILE
-#endif
-
-#define IDS_LATE_RUN_AP_TASK
-
-#define M_HTIDS_PORT_OVERRIDE_HOOK (PF_HtIdsGetPortOverride)CommonVoid
-#if (IDSOPT_IDS_ENABLED == TRUE)
-  #if (IDSOPT_CONTROL_ENABLED == TRUE)
-    // Check for all families which include HT Features.
-  #endif
-#endif // OPTION_IDS_LEVEL
-CONST PF_HtIdsGetPortOverride ROMDATA pf_HtIdsGetPortOverride = M_HTIDS_PORT_OVERRIDE_HOOK;
-
-#if (IDSOPT_IDS_ENABLED == TRUE)
-  #if (AGESA_ENTRY_INIT_LATE == TRUE)
-    #undef IDS_LATE_RUN_AP_TASK
-    #define IDS_LATE_RUN_AP_TASK
-  #endif
-#endif // OPTION_IDS_LEVEL
-
-#if (IDSOPT_TRACING_ENABLED == TRUE)
-  #if (AGESA_ENTRY_INIT_POST == TRUE)
-    #include <mu.h>
-    CONST SCRIPT_FUNCTION ROMDATA ScriptFuncList[] = {
-      { (UINTN) MemUWriteCachelines, "WriteCl(PhyAddrLo,BufferAddr,ClCnt)"},
-      { (UINTN) MemUReadCachelines, "ReadCl(BufferAddr,PhyAddrLo,ClCnt)"},
-      { (UINTN) MemUFlushPattern, "FlushCl(PhyAddrLo,ClCnt)"}
-    };
-  #else
-    CONST SCRIPT_FUNCTION ROMDATA ScriptFuncList[] = {
-      { (UINTN) CommonReturnFalse, "DefRet()"},
-      { (UINTN) CommonReturnFalse, "DefRet()"},
-      { (UINTN) CommonReturnFalse, "DefRet()"}
-    };
-  #endif
-#endif
-
-
-///Ids Feat Options
-#if (IDSOPT_IDS_ENABLED == TRUE)
-  #if (IDSOPT_CONTROL_ENABLED == TRUE)
-
-    #ifndef OPTION_IDS_EXTEND_FEATS
-      #define OPTION_IDS_EXTEND_FEATS
-    #endif
-
-    #define OPTION_IDS_FEAT_GNB_PLATFORMCFG\
-                OPTION_IDS_FEAT_GNB_PLATFORMCFGF14
-
-/*----------------------------------------------------------------------------
- *                        Family 14 feat blocks
- *
- *----------------------------------------------------------------------------
- */
-    #define OPTION_IDS_FEAT_GNB_PLATFORMCFGF14
-    #ifdef OPTION_FAMILY14H
-      #if OPTION_FAMILY14H == TRUE
-        extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatGnbPlatformCfgBlockF14;
-        #undef OPTION_IDS_FEAT_GNB_PLATFORMCFGF14
-        #define OPTION_IDS_FEAT_GNB_PLATFORMCFGF14 &IdsFeatGnbPlatformCfgBlockF14,
-      #endif
-    #endif
-
-    CONST IDS_FEAT_STRUCT ROMDATA IdsFeatUcodeBlock =
-    {
-      IDS_FEAT_UCODE_UPDATE,
-      IDS_ALL_CORES,
-      IDS_UCODE,
-      IDS_FAMILY_ALL,
-      IdsSubUCode
-    };
-
-    CONST IDS_FEAT_STRUCT ROMDATA IdsFeatPowerPolicyBlock =
-    {
-      IDS_FEAT_POWER_POLICY,
-      IDS_ALL_CORES,
-      IDS_PLATFORMCFG_OVERRIDE,
-      IDS_FAMILY_ALL,
-      IdsSubPowerPolicyOverride
-    };
-
-    CONST IDS_FEAT_STRUCT ROMDATA IdsFeatTargetPstateBlock =
-    {
-      IDS_FEAT_TARGET_PSTATE,
-      IDS_BSP_ONLY,
-      IDS_INIT_LATE_AFTER,
-      IDS_FAMILY_ALL,
-      IdsSubTargetPstate
-    };
-
-    CONST IDS_FEAT_STRUCT ROMDATA IdsFeatPostPstateBlock =
-    {
-      IDS_FEAT_POSTPSTATE,
-      IDS_ALL_CORES,
-      IDS_CPU_Early_Override,
-      IDS_FAMILY_ALL,
-      IdsSubPostPState
-    };
-
-    //Dram controller Features
-    CONST IDS_FEAT_STRUCT ROMDATA IdsFeatDctAllMemClkBlock =
-    {
-      IDS_FEAT_DCT_ALLMEMCLK,
-      IDS_BSP_ONLY,
-      IDS_ALL_MEMORY_CLOCK,
-      IDS_FAMILY_ALL,
-      IdsSubAllMemClkEn
-    };
-
-    CONST IDS_FEAT_STRUCT ROMDATA IdsFeatDctGangModeBlock =
-    {
-      IDS_FEAT_DCT_GANGMODE,
-      IDS_BSP_ONLY,
-      IDS_GANGING_MODE,
-      IDS_FAMILY_ALL,
-      IdsSubGangingMode
-    };
-
-    CONST IDS_FEAT_STRUCT ROMDATA IdsFeatDctBurstLengthBlock =
-    {
-      IDS_FEAT_DCT_BURSTLENGTH,
-      IDS_BSP_ONLY,
-      IDS_BURST_LENGTH32,
-      AMD_FAMILY_10,
-      IdsSubBurstLength32
-    };
-
-    CONST IDS_FEAT_STRUCT ROMDATA IdsFeatDctPowerDownCtrlBlock =
-    {
-      IDS_FEAT_DCT_POWERDOWN,
-      IDS_BSP_ONLY,
-      IDS_INIT_POST_BEFORE,
-      IDS_FAMILY_ALL,
-      IdsSubPowerDownCtrl
-    };
-
-    CONST IDS_FEAT_STRUCT ROMDATA IdsFeatDctDllShutDownBlock =
-    {
-      IDS_FEAT_DCT_DLLSHUTDOWN,
-      IDS_BSP_ONLY,
-      IDS_DLL_SHUT_DOWN,
-      IDS_FAMILY_ALL,
-      IdsSubDllShutDownSR
-    };
-
-
-    CONST IDS_FEAT_STRUCT ROMDATA IdsFeatDctPowerDownModeBlock =
-    {
-      IDS_FEAT_DCT_POWERDOWN,
-      IDS_BSP_ONLY,
-      IDS_POWERDOWN_MODE,
-      IDS_FAMILY_ALL,
-      IdsSubPowerDownMode
-    };
-
-    CONST IDS_FEAT_STRUCT ROMDATA IdsFeatHdtOutBlock =
-    {
-      IDS_FEAT_HDTOUT,
-      IDS_BSP_ONLY,
-      IDS_INIT_EARLY_BEFORE,
-      IDS_FAMILY_ALL,
-      IdsSubHdtOut
-    };
-
-    CONST IDS_FEAT_STRUCT ROMDATA IdsFeatHtSettingBlock =
-    {
-      IDS_FEAT_HT_SETTING,
-      IDS_BSP_ONLY,
-      IDS_HT_CONTROL,
-      IDS_FAMILY_ALL,
-      IdsSubHtLinkControl
-    };
-
-    CONST IDS_FEAT_STRUCT* ROMDATA IdsCommonFeats[] =
-    {
-      &IdsFeatUcodeBlock,
-      &IdsFeatPowerPolicyBlock,
-
-      &IdsFeatTargetPstateBlock,
-
-      &IdsFeatPostPstateBlock,
-
-      OPTION_IDS_FEAT_ECCSYMBOLSIZE
-
-      OPTION_IDS_FEAT_ECCCTRL
-
-      &IdsFeatDctAllMemClkBlock,
-
-      &IdsFeatDctGangModeBlock,
-
-      &IdsFeatDctBurstLengthBlock,
-
-      &IdsFeatDctPowerDownCtrlBlock,
-
-      &IdsFeatDctPowerDownModeBlock,
-
-      &IdsFeatDctPowerDownModeBlock,
-
-      OPTION_IDS_FEAT_HT_ASSIST
-
-      &IdsFeatHdtOutBlock,
-
-      &IdsFeatHtSettingBlock,
-
-      OPTION_IDS_FEAT_GNB_PLATFORMCFG
-
-      OPTION_IDS_FEAT_CPB_CTRL
-
-      OPTION_IDS_FEAT_HTC_CTRL
-
-      OPTION_IDS_FEAT_MEMORY_MAPPING
-
-      OPTION_IDS_EXTEND_FEATS
-
-      NULL
-    };
-  #else
-    CONST IDS_FEAT_STRUCT* ROMDATA IdsCommonFeats[] =
-    {
-      NULL
-    };
-  #endif//IDSOPT_CONTROL_ENABLED
-#else
-  CONST IDS_FEAT_STRUCT* ROMDATA IdsCommonFeats[] =
-  {
-    NULL
-  };
-#endif// IDSOPT_IDS_ENABLED
-
-
-#endif
diff --git a/src/vendorcode/amd/agesa/f14/Config/OptionIoCstateInstall.h b/src/vendorcode/amd/agesa/f14/Config/OptionIoCstateInstall.h
deleted file mode 100644
index 25caa82e14ce..000000000000
--- a/src/vendorcode/amd/agesa/f14/Config/OptionIoCstateInstall.h
+++ /dev/null
@@ -1,91 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: IO C-state
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Options
- * @e \$Revision: 34897 $   @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _OPTION_IO_CSTATE_INSTALL_H_
-#define _OPTION_IO_CSTATE_INSTALL_H_
-
-#include "cpuIoCstate.h"
-
-/*  This option is designed to be included into the platform solution install
- *  file. The platform solution install file will define the options status.
- *  Check to validate the definition
- */
-
-#define OPTION_IO_CSTATE_FEAT
-#define F14_IO_CSTATE_SUPPORT
-
-#if OPTION_IO_CSTATE == TRUE
-  #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE)
-
-    #ifdef OPTION_FAMILY14H
-      #if OPTION_FAMILY14H == TRUE
-        #if OPTION_FAMILY14H_ON == TRUE
-          extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureIoCstate;
-          #undef OPTION_IO_CSTATE_FEAT
-          #define OPTION_IO_CSTATE_FEAT &CpuFeatureIoCstate,
-          extern CONST IO_CSTATE_FAMILY_SERVICES ROMDATA F14IoCstateSupport;
-          #undef F14_IO_CSTATE_SUPPORT
-          #define F14_IO_CSTATE_SUPPORT {AMD_FAMILY_14_ON, &F14IoCstateSupport},
-        #endif
-      #endif
-    #endif
-
-  #endif
-#endif
-
-CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA IoCstateFamilyServiceArray[] =
-{
-  F14_IO_CSTATE_SUPPORT
-  {0, NULL}
-};
-
-CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA IoCstateFamilyServiceTable =
-{
-  (sizeof (IoCstateFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
-  &IoCstateFamilyServiceArray[0]
-};
-
-#endif // _OPTION_IO_CSTATE_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f14/Config/OptionLowPwrPstateInstall.h b/src/vendorcode/amd/agesa/f14/Config/OptionLowPwrPstateInstall.h
deleted file mode 100644
index ed2465814e76..000000000000
--- a/src/vendorcode/amd/agesa/f14/Config/OptionLowPwrPstateInstall.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: Low Power Pstate for PROCHOT_L Throttling.
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Options
- * @e \$Revision: 34897 $   @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _OPTION_LOW_PWR_PSTATE_INSTALL_H_
-#define _OPTION_LOW_PWR_PSTATE_INSTALL_H_
-
-#include "cpuLowPwrPstate.h"
-
-/*  This option is designed to be included into the platform solution install
- *  file. The platform solution install file will define the options status.
- *  Check to validate the definition
- */
-#define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT_FEAT
-
-#if OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT == TRUE
-  #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE)
-  #endif
-#endif
-
-CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA LowPwrPstateFamilyServiceArray[] =
-{
-  {0, NULL}
-};
-
-CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA LowPwrPstateFamilyServiceTable =
-{
-  (sizeof (LowPwrPstateFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
-  &LowPwrPstateFamilyServiceArray[0]
-};
-
-#endif  // _OPTION_LOW_PWR_PSTATE_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f14/Config/OptionMemoryInstall.h b/src/vendorcode/amd/agesa/f14/Config/OptionMemoryInstall.h
deleted file mode 100644
index 367ad62226c1..000000000000
--- a/src/vendorcode/amd/agesa/f14/Config/OptionMemoryInstall.h
+++ /dev/null
@@ -1,784 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: Memory
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Options
- * @e \$Revision: 37402 $   @e \$Date: 2010-09-03 05:36:02 +0800 (Fri, 03 Sep 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _OPTION_MEMORY_INSTALL_H_
-#define _OPTION_MEMORY_INSTALL_H_
-
-/*-------------------------------------------------------------------------------
- *  This option file is designed to be included into the platform solution install
- *  file. The platform solution install file will define the options status.
- *  Check to validate the definition
- */
-
-/*----------------------------------------------------------------------------------
- * FEATURE BLOCK FUNCTIONS
- *
- *  This section defines function names that depend upon options that are selected
- *  in the platform solution install file.
- */
-BOOLEAN MemFDefRet (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  return FALSE;
-}
-
-BOOLEAN MemMDefRet (
-  IN   MEM_MAIN_DATA_BLOCK *MMPtr
-  )
-{
-  return TRUE;
-}
-
-BOOLEAN MemMDefRetFalse (
-  IN   MEM_MAIN_DATA_BLOCK *MMPtr
-  )
-{
-  return FALSE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function initializes the northbridge block for dimm identification translator
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *     @param[in,out]   *MemPtr  - Pointer to the MEM_DATA_STRUCT
- *     @param[in,out]   NodeID   - ID of current node to construct
- *     @return          TRUE     - This is the correct constructor for the targeted node.
- *     @return          FALSE    - This isn't the correct constructor for the targeted node.
- */
-BOOLEAN MemNIdentifyDimmConstructorRetDef (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN OUT   MEM_DATA_STRUCT *MemPtr,
-  IN       UINT8 NodeID
-  )
-{
-  return FALSE;
-}
-/*----------------------------------------------------------------------------------
- * TABLE FEATURE BLOCK FUNCTIONS
- *
- *  This section defines function names that depend upon options that are selected
- *  in the platform solution install file.
- */
-UINT8 MemFTableDefRet (
-  IN OUT   MEM_TABLE_ALIAS **MTPtr
-  )
-{
-  return 0;
-}
-/*----------------------------------------------------------------------------------
- * FEATURE S3 BLOCK FUNCTIONS
- *
- *  This section defines function names that depend upon options that are selected
- *  in the platform solution install file.
- */
-BOOLEAN MemFS3DefConstructorRet (
-  IN OUT   VOID *S3NBPtr,
-  IN OUT   MEM_DATA_STRUCT *MemPtr,
-  IN       UINT8 NodeID
-  )
-{
-  return TRUE;
-}
-
-#if (OPTION_MEMCTLR_ON == TRUE)
-  #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE))
-    #if (OPTION_S3_MEM_SUPPORT == TRUE)
-      extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockON;
-      #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_ON MemS3ResumeConstructNBBlockON
-    #else
-      #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_ON MemFS3DefConstructorRet
-    #endif
-  #else
-    #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_ON MemFS3DefConstructorRet
-  #endif
-  #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE)
-    extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorON;
-    #define MEM_IDENDIMM_ON MemNIdentifyDimmConstructorON
-  #else
-    #define MEM_IDENDIMM_ON MemNIdentifyDimmConstructorRetDef
-  #endif
-#endif
-
-/*----------------------------------------------------------------------------------
- * NORTHBRIDGE BLOCK CONSTRUCTOR AND INITIALIZER FUNCTION DEFAULT ASSIGNMENTS
- *
- *----------------------------------------------------------------------------------
-*/
-#define MEM_NB_SUPPORT_ON
-#define MEM_NB_SUPPORT_END { MEM_NB_SUPPORT_STRUCT_VERSION, 0, 0, 0, 0, 0 }
-
-#if (AGESA_ENTRY_INIT_POST == TRUE)
-  /*----------------------------------------------------------------------------------
-   * FLOW CONTROL FUNCTION
-   *
-   *  This section selects the function that controls the memory initialization sequence
-   *  based upon the number of processor families that the BIOS will support.
-   */
-
-  extern MEM_FLOW_CFG MemMFlowDef;
-
-  #if (OPTION_MEMCTLR_ON == TRUE)
-    extern MEM_FLOW_CFG MemMFlowON;
-    #define MEM_MAIN_FLOW_CONTROL_PTR_ON MemMFlowON,
-  #else
-    #define MEM_MAIN_FLOW_CONTROL_PTR_ON MemMFlowDef,
-  #endif
-
-  MEM_FLOW_CFG* CONST memFlowControlInstalled[] = {
-    MEM_MAIN_FLOW_CONTROL_PTR_ON
-    NULL
-  };
-
-  #if (OPTION_ONLINE_SPARE == TRUE)
-    extern OPTION_MEM_FEATURE_MAIN MemMOnlineSpare;
-    #define MEM_MAIN_FEATURE_ONLINE_SPARE  MemMOnlineSpare
-    extern OPTION_MEM_FEATURE_NB MemFOnlineSpare;
-    #define MEM_FEATURE_ONLINE_SPARE  MemFOnlineSpare
-  #else
-    #define MEM_MAIN_FEATURE_ONLINE_SPARE  MemMDefRet
-    #define MEM_FEATURE_ONLINE_SPARE  MemFDefRet
-  #endif
-
-  #if (OPTION_MEM_RESTORE == TRUE)
-    extern OPTION_MEM_FEATURE_MAIN MemMContextSave;
-    extern OPTION_MEM_FEATURE_MAIN MemMContextRestore;
-    #define MEM_MAIN_FEATURE_MEM_SAVE     MemMContextSave
-    #define MEM_MAIN_FEATURE_MEM_RESTORE  MemMContextRestore
-  #else
-    #define MEM_MAIN_FEATURE_MEM_SAVE     MemMDefRet
-    #define MEM_MAIN_FEATURE_MEM_RESTORE  MemMDefRetFalse
-  #endif
-
-  #if (OPTION_BANK_INTERLEAVE == TRUE)
-    extern OPTION_MEM_FEATURE_NB MemFInterleaveBanks;
-    #define MEM_FEATURE_BANK_INTERLEAVE  MemFInterleaveBanks
-    extern OPTION_MEM_FEATURE_NB MemFUndoInterleaveBanks;
-    #define MEM_FEATURE_UNDO_BANK_INTERLEAVE MemFUndoInterleaveBanks
-  #else
-    #define MEM_FEATURE_BANK_INTERLEAVE  MemFDefRet
-    #define MEM_FEATURE_UNDO_BANK_INTERLEAVE MemFDefRet
-  #endif
-
-  #if (OPTION_NODE_INTERLEAVE == TRUE)
-    extern OPTION_MEM_FEATURE_MAIN MemMInterleaveNodes;
-    #define MEM_MAIN_FEATURE_NODE_INTERLEAVE  MemMInterleaveNodes
-    extern OPTION_MEM_FEATURE_NB MemFCheckInterleaveNodes;
-    extern OPTION_MEM_FEATURE_NB MemFInterleaveNodes;
-    #define MEM_FEATURE_NODE_INTERLEAVE_CHECK  MemFCheckInterleaveNodes
-    #define MEM_FEATURE_NODE_INTERLEAVE  MemFInterleaveNodes
-  #else
-    #define MEM_FEATURE_NODE_INTERLEAVE_CHECK  MemFDefRet
-    #define MEM_FEATURE_NODE_INTERLEAVE  MemFDefRet
-    #define MEM_MAIN_FEATURE_NODE_INTERLEAVE  MemMDefRet
-  #endif
-
-  #if (OPTION_DCT_INTERLEAVE == TRUE)
-    extern OPTION_MEM_FEATURE_NB MemFInterleaveChannels;
-    #define MEM_FEATURE_CHANNEL_INTERLEAVE  MemFInterleaveChannels
-  #else
-    #define MEM_FEATURE_CHANNEL_INTERLEAVE  MemFDefRet
-  #endif
-
-  #if (OPTION_ECC == TRUE)
-    extern OPTION_MEM_FEATURE_MAIN MemMEcc;
-    #define MEM_MAIN_FEATURE_ECC  MemMEcc
-    extern OPTION_MEM_FEATURE_NB MemFCheckECC;
-    extern OPTION_MEM_FEATURE_NB MemFInitECC;
-    #define MEM_FEATURE_CK_ECC   MemFCheckECC
-    #define MEM_FEATURE_ECC   MemFInitECC
-    #define MEM_FEATURE_ECCX8  MemMDefRet
-  #else
-    #define MEM_MAIN_FEATURE_ECC  MemMDefRet
-    #define MEM_FEATURE_CK_ECC   MemFDefRet
-    #define MEM_FEATURE_ECC   MemFDefRet
-    #define MEM_FEATURE_ECCX8  MemMDefRet
-  #endif
-
-  extern OPTION_MEM_FEATURE_MAIN MemMMctMemClr;
-  #define MEM_MAIN_FEATURE_MEM_CLEAR  MemMMctMemClr
-
-  #if (OPTION_DMI == TRUE)
-    #if (OPTION_DDR3 == TRUE)
-      extern OPTION_MEM_FEATURE_MAIN MemFDMISupport3;
-      #define MEM_MAIN_FEATURE_MEM_DMI MemFDMISupport3
-    #else
-      extern OPTION_MEM_FEATURE_MAIN MemFDMISupport2;
-      #define MEM_MAIN_FEATURE_MEM_DMI MemFDMISupport2
-    #endif
-  #else
-    #define MEM_MAIN_FEATURE_MEM_DMI MemMDefRet
-  #endif
-
-  #if (OPTION_DDR3 == TRUE)
-    extern OPTION_MEM_FEATURE_NB MemFOnDimmThermal;
-    extern OPTION_MEM_FEATURE_MAIN MemMLvDdr3;
-    extern OPTION_MEM_FEATURE_NB MemFLvDdr3;
-    #define MEM_FEATURE_ONDIMMTHERMAL MemFOnDimmThermal
-    #define MEM_MAIN_FEATURE_LVDDR3 MemMLvDdr3
-    #define MEM_FEATURE_LVDDR3 MemFLvDdr3
-  #else
-    #define MEM_FEATURE_ONDIMMTHERMAL MemFDefRet
-    #define MEM_MAIN_FEATURE_LVDDR3 MemMDefRet
-    #define MEM_FEATURE_LVDDR3 MemFDefRet
-  #endif
-
-  extern OPTION_MEM_FEATURE_NB MemFInterleaveRegion;
-  #define MEM_FEATURE_REGION_INTERLEAVE    MemFInterleaveRegion
-
-  extern OPTION_MEM_FEATURE_MAIN MemMUmaAlloc;
-  #define MEM_MAIN_FEATURE_UMAALLOC   MemMUmaAlloc
-
-  extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining;
-  #if (OPTION_PARALLEL_TRAINING == TRUE)
-    extern OPTION_MEM_FEATURE_MAIN MemMParallelTraining;
-    #define MEM_MAIN_FEATURE_TRAINING  MemMParallelTraining
-  #else
-    #define MEM_MAIN_FEATURE_TRAINING  MemMStandardTraining
-  #endif
-
-  #if (OPTION_DIMM_EXCLUDE == TRUE)
-    extern OPTION_MEM_FEATURE_MAIN MemMRASExcludeDIMM;
-    #define MEM_MAIN_FEATURE_DIMM_EXCLUDE  MemMRASExcludeDIMM
-    extern OPTION_MEM_FEATURE_NB MemFRASExcludeDIMM;
-    #define MEM_FEATURE_DIMM_EXCLUDE  MemFRASExcludeDIMM
-  #else
-    #define MEM_FEATURE_DIMM_EXCLUDE  MemFDefRet
-    #define MEM_MAIN_FEATURE_DIMM_EXCLUDE  MemMDefRet
-  #endif
-
-  /*----------------------------------------------------------------------------------
-   * TECHNOLOGY BLOCK CONSTRUCTOR FUNCTION ASSIGNMENTS
-   *
-   *----------------------------------------------------------------------------------
-  */
-  #if OPTION_DDR3 == TRUE
-    extern MEM_TECH_CONSTRUCTOR MemConstructTechBlock3;
-    #define MEM_TECH_CONSTRUCTOR_DDR3 MemConstructTechBlock3,
-    #if (OPTION_HW_DRAM_INIT == TRUE)
-      extern MEM_TECH_FEAT MemTDramInitHw;
-      #define MEM_TECH_FEATURE_HW_DRAMINIT  MemTDramInitHw
-    #else
-      #define  MEM_TECH_FEATURE_HW_DRAMINIT MemTFeatDef
-    #endif
-    #if (OPTION_SW_DRAM_INIT == TRUE)
-//      extern MEM_TECH_FEAT MemTDramInitSw3;
-      #define MEM_TECH_FEATURE_SW_DRAMINIT  MemTDramInitSw3
-    #else
-      #define MEM_TECH_FEATURE_SW_DRAMINIT  MemTFeatDef
-    #endif
-  #else
-    #define MEM_TECH_CONSTRUCTOR_DDR3
-  #endif
-
-  /*---------------------------------------------------------------------------------------------------
-   * FEATURE BLOCKS
-   *
-   *  This section instantiates a feature block structure for each memory controller installed
-   *  by the platform solution install file.
-   *---------------------------------------------------------------------------------------------------
-   */
-
-  /*---------------------------------------------------------------------------------------------------
-   * ONTARIO FEATURE BLOCK
-   *---------------------------------------------------------------------------------------------------
-   */
-  #if (OPTION_MEMCTLR_ON == TRUE)
-    #if OPTION_DDR3
-      #undef MEM_TECH_FEATURE_DRAMINIT
-      #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT
-    #endif
-
-    #if (OPTION_CONTINOUS_PATTERN_GENERATION == TRUE)
-      extern OPTION_MEM_FEATURE_NB MemNInitCPGClientNb;
-      #undef MEM_TECH_FEATURE_CPG
-      #define MEM_TECH_FEATURE_CPG    MemNInitCPGClientNb
-    #else
-      #undef MEM_TECH_FEATURE_CPG
-      #define MEM_TECH_FEATURE_CPG    MemFDefRet
-    #endif
-
-    #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
-      extern OPTION_MEM_FEATURE_NB MemNInitDqsTrainRcvrEnHwNb;
-      #undef MEM_TECH_FEATURE_HWRXEN
-      #define MEM_TECH_FEATURE_HWRXEN    MemNInitDqsTrainRcvrEnHwNb
-    #else
-      extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb;
-      #undef MEM_TECH_FEATURE_HWRXEN
-      #define MEM_TECH_FEATURE_HWRXEN    MemNDisableDqsTrainRcvrEnHwNb
-    #endif
-
-    #undef MEM_MAIN_FEATURE_TRAINING
-    #undef MEM_FEATURE_TRAINING
-    #define MEM_MAIN_FEATURE_TRAINING  MemMStandardTraining
-    extern OPTION_MEM_FEATURE_NB MemFStandardTraining;
-    #define MEM_FEATURE_TRAINING  MemFStandardTraining
-
-    #if (OPTION_EARLY_SAMPLES == TRUE)
-      extern OPTION_MEM_FEATURE_NB MemNInitEarlySampleSupportON;
-      #define MEM_EARLY_SAMPLE_SUPPORT    MemNInitEarlySampleSupportON
-    #else
-      #define MEM_EARLY_SAMPLE_SUPPORT    MemFDefRet
-    #endif
-
-    CONST MEM_FEAT_BLOCK_NB  MemFeatBlockOn = {
-      MEM_FEAT_BLOCK_NB_STRUCT_VERSION,
-      MemFDefRet,
-      MEM_FEATURE_BANK_INTERLEAVE,
-      MEM_FEATURE_UNDO_BANK_INTERLEAVE,
-      MemFDefRet,
-      MemFDefRet,
-      MemFDefRet,
-      MemFDefRet,
-      MemFDefRet,
-      MemFDefRet,
-      MEM_FEATURE_TRAINING,
-      MEM_FEATURE_LVDDR3,
-      MEM_FEATURE_ONDIMMTHERMAL,
-      MEM_TECH_FEATURE_DRAMINIT,
-      MEM_FEATURE_DIMM_EXCLUDE,
-      MEM_EARLY_SAMPLE_SUPPORT,
-      MEM_TECH_FEATURE_CPG,
-      MEM_TECH_FEATURE_HWRXEN
-    };
-
-    #undef MEM_NB_SUPPORT_ON
-    extern MEM_NB_CONSTRUCTOR MemConstructNBBlockON;
-    extern MEM_INITIALIZER MemNInitDefaultsON;
-    #define MEM_NB_SUPPORT_ON { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockON, MemNInitDefaultsON, &MemFeatBlockOn, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_ON, MEM_IDENDIMM_ON },
-
-  #endif // OPTION_MEMCTRL_ON
-
-  /*---------------------------------------------------------------------------------------------------
-   * MAIN FEATURE BLOCK
-   *---------------------------------------------------------------------------------------------------
-   */
-  CONST MEM_FEAT_BLOCK_MAIN MemFeatMain = {
-    MEM_FEAT_BLOCK_MAIN_STRUCT_VERSION,
-    MEM_MAIN_FEATURE_TRAINING,
-    MEM_MAIN_FEATURE_DIMM_EXCLUDE,
-    MEM_MAIN_FEATURE_ONLINE_SPARE,
-    MEM_MAIN_FEATURE_NODE_INTERLEAVE,
-    MEM_MAIN_FEATURE_ECC,
-    MEM_MAIN_FEATURE_MEM_CLEAR,
-    MEM_MAIN_FEATURE_MEM_DMI,
-    MEM_MAIN_FEATURE_LVDDR3,
-    MEM_MAIN_FEATURE_UMAALLOC,
-    MEM_MAIN_FEATURE_MEM_SAVE,
-    MEM_MAIN_FEATURE_MEM_RESTORE
-  };
-
-
-  /*---------------------------------------------------------------------------------------------------
-   * Technology Training SPECIFIC CONFIGURATION
-   *
-   *
-   *---------------------------------------------------------------------------------------------------
-   */
-
-  #if OPTION_MEMCTLR_ON
-    extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceON;
-    #if OPTION_DDR3
-      #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
-      #define TECH_TRAIN_ENTER_HW_TRN_DDR3   MemTFeatDef
-      #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
-      #define TECH_TRAIN_EXIT_HW_TRN_DDR3    MemTExitPhyAssistedTrainingClient3
-      #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE)
-        #define TECH_TRAIN_HW_WL_P1_DDR3   MemTWriteLevelizationHw3Pass1
-        #define TECH_TRAIN_HW_WL_P2_DDR3   MemTWriteLevelizationHw3Pass2
-      #else
-        #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
-        #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
-      #endif
-      #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
-      #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
-        #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3    MemTDqsTrainRcvrEnHwPass1
-        #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3    MemTDqsTrainRcvrEnHwPass2
-      #else
-        #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
-        #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
-      #endif
-      #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
-        #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3    MemTTrainRcvrEnSwPass1
-      #else
-        #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
-      #endif
-      #undef TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3
-      #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
-        #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3    MemTTrainOptRcvrEnSwPass1
-      #else
-        #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
-      #endif
-      #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
-        #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
-      #else
-        #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
-      #endif
-      #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
-        #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
-      #else
-        #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
-      #endif
-      #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
-        #define TECH_TRAIN_MAX_RD_LAT_DDR3    MemTTrainMaxLatency
-      #else
-        #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
-      #endif
-      CONST MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR3ON = {
-        MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
-        TECH_TRAIN_ENTER_HW_TRN_DDR3,
-        TECH_TRAIN_SW_WL_DDR3,
-        TECH_TRAIN_HW_WL_P1_DDR3,
-        TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3,
-        TECH_TRAIN_HW_WL_P2_DDR3,
-        TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3,
-        TECH_TRAIN_EXIT_HW_TRN_DDR3,
-        TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3,
-        TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3,
-        TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3,
-        TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3,
-        TECH_TRAIN_MAX_RD_LAT_DDR3
-      };
-//      extern OPTION_MEM_FEATURE_NB MemNDQSTiming3Nb;
-      #define NB_TRAIN_FLOW_DDR3    MemNDQSTiming3Nb
-//      extern OPTION_MEM_FEATURE_NB memNSequenceDDR3Nb;
-      #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_ON {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR3Nb, memNEnableTrainSequenceON, &memTechTrainingFeatSequenceDDR3ON },
-    #else
-      #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
-      #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef
-      #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
-      #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef
-      #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
-      #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
-      #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
-      #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
-      #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
-      #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
-      #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
-      #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
-      #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
-      #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
-      #define NB_TRAIN_FLOW_DDR3    (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
-      #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_ON  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
-    #endif
-  #else
-    #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_ON  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
-  #endif
-
-  #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_END { MEM_NB_SUPPORT_STRUCT_VERSION, 0, 0, 0 }
-
-  CONST MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[] = {
-    MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_ON
-    MEM_TECH_ENABLE_TRAINING_SEQUENCE_END
-  };
-  /*---------------------------------------------------------------------------------------------------
-   * NB TRAINING FLOW CONTROL
-   *
-   *
-   *---------------------------------------------------------------------------------------------------
-   */
-  #define NB_TRAIN_FLOW_DDR2    (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
-
-  OPTION_MEM_FEATURE_NB* CONST memNTrainFlowControl[] = {    // Training flow control
-    NB_TRAIN_FLOW_DDR2,
-    NB_TRAIN_FLOW_DDR3,
-  };
-  /*---------------------------------------------------------------------------------------------------
-   * TECHNOLOGY BLOCK
-   *
-   *
-   *---------------------------------------------------------------------------------------------------
-   */
-  MEM_TECH_CONSTRUCTOR* CONST memTechInstalled[] = {    // Types of technology installed
-    MEM_TECH_CONSTRUCTOR_DDR3
-    NULL
-  };
-   /*---------------------------------------------------------------------------------------------------
-   * PLATFORM SPECIFIC BLOCK FORM FACTOR DEFINITION
-   *
-   *
-   *---------------------------------------------------------------------------------------------------
-   */
-
-  #if OPTION_MEMCTLR_ON
-    #if OPTION_UDIMMS
-      #if OPTION_DDR3
-        #define PLAT_SP_ON_FF_UDIMM3    MemPConstructPsUON3,
-      #else
-        #define PLAT_SP_ON_FF_UDIMM3    MemPConstructPsUDef,
-      #endif
-    #else
-      #define PLAT_SP_ON_FF_UDIMM3    MemPConstructPsUDef,
-    #endif
-    #if OPTION_SODIMMS
-      #if OPTION_DDR3
-        #define PLAT_SP_ON_FF_SDIMM3    MemPConstructPsSON3,
-      #else
-        #define PLAT_SP_ON_FF_SDIMM3    MemPConstructPsUDef,
-      #endif
-    #else
-      #define PLAT_SP_ON_FF_SDIMM3    MemPConstructPsUDef,
-    #endif
-  #else
-    #define PLAT_SP_ON_FF_SDIMM3    MemPConstructPsUDef,
-    #define PLAT_SP_ON_FF_UDIMM3    MemPConstructPsUDef,
-  #endif
-  MEM_PLAT_SPEC_CFG* CONST memPlatSpecFFInstalledON[MAX_FF_TYPES] = {
-    PLAT_SP_ON_FF_SDIMM3
-    PLAT_SP_ON_FF_UDIMM3
-    NULL
-  };
-
-  /*---------------------------------------------------------------------------------------------------
-   * PLATFORM-SPECIFIC CONFIGURATION
-   *
-   *
-   *---------------------------------------------------------------------------------------------------
-   */
-
-  #if OPTION_MEMCTLR_ON
-    #if OPTION_UDIMMS
-      #if OPTION_DDR3
-        #define PSC_ON_UDIMM_DDR3    MemAGetPsCfgUON3,
-      #else
-        #define PSC_ON_UDIMM_DDR3
-      #endif
-    #endif
-    #if OPTION_RDIMMS
-      #if OPTION_DDR3
-        #define PSC_ON_RDIMM_DDR3    //MemAGetPsCfgRON3,
-      #else
-        #define PSC_ON_RDIMM_DDR3
-      #endif
-    #endif
-    #if OPTION_SODIMMS
-      #if OPTION_DDR3
-        #define PSC_ON_SODIMM_DDR3   MemAGetPsCfgSON3,
-      #else
-        #define PSC_ON_SODIMM_DDR3
-      #endif
-    #endif
-  #endif
-
-  /*----------------------------------------------------------------------
-   * DEFAULT PSCFG DEFINITIONS
-   *
-   *----------------------------------------------------------------------
-   */
-
-  #ifndef PSC_ON_UDIMM_DDR3
-    #define PSC_ON_UDIMM_DDR3
-  #endif
-  #ifndef PSC_ON_RDIMM_DDR3
-    #define PSC_ON_RDIMM_DDR3
-  #endif
-  #ifndef PSC_ON_SODIMM_DDR3
-    #define PSC_ON_SODIMM_DDR3
-  #endif
-
-  MEM_PLATFORM_CFG* CONST memPlatformTypeInstalled[] = {
-    PSC_ON_UDIMM_DDR3
-    PSC_ON_RDIMM_DDR3
-    PSC_ON_SODIMM_DDR3
-    NULL
-  };
-  CONST UINTN SIZE_OF_PLATFORM = (sizeof (memPlatformTypeInstalled) / sizeof (MEM_PLATFORM_CFG*));
-//  #if SIZE_OF_PLATFORM > MAX_PLATFORM_TYPES
-//    #error   Size of memPlatformTypeInstalled array larger than MAX_PLATFORM_TYPES
-//  #endif
-
-  /*---------------------------------------------------------------------------------------------------
-   * EXTRACTABLE PLATFORM SPECIFIC CONFIGURATION
-   *
-   *
-   *---------------------------------------------------------------------------------------------------
-   */
-  #define MEM_PSC_FLOW_BLOCK_END NULL
-  #define PSC_TBL_END NULL
-  #define MEM_PSC_FLOW_DEFTRUE (BOOLEAN (*) (MEM_NB_BLOCK*, MEM_PSC_TABLE_BLOCK *)) memDefTrue
-
-
-  MEM_PSC_FLOW_BLOCK* CONST memPlatSpecFlowArray[] = {
-    MEM_PSC_FLOW_BLOCK_END
-  };
-
-  /*---------------------------------------------------------------------------------------------------
-  *
-  *  LRDIMM CONTROL
-  *
-  *---------------------------------------------------------------------------------------------------
-  */
-  #if (OPTION_LRDIMMS == TRUE)
-    #define MEM_TECH_FEATURE_LRDIMM_INIT    MemTFeatDef
-  #else //#if (OPTION_LRDIMMS == FALSE)
-    #define MEM_TECH_FEATURE_LRDIMM_INIT    MemTFeatDef
-  #endif
-  CONST MEM_TECH_LRDIMM memLrdimmSupported = {
-    MEM_TECH_LRDIMM_STRUCT_VERSION,
-    MEM_TECH_FEATURE_LRDIMM_INIT
-  };
-#else
-  /*---------------------------------------------------------------------------------------------------
-   * MAIN FLOW CONTROL
-   *
-   *
-   *---------------------------------------------------------------------------------------------------
-   */
-  MEM_FLOW_CFG* CONST memFlowControlInstalled[] = {
-    NULL
-  };
-  /*---------------------------------------------------------------------------------------------------
-   * NB TRAINING FLOW CONTROL
-   *
-   *
-   *---------------------------------------------------------------------------------------------------
-   */
-  OPTION_MEM_FEATURE_NB* CONST memNTrainFlowControl[] = {    // Training flow control
-    NULL,
-    NULL,
-  };
-  /*---------------------------------------------------------------------------------------------------
-   * DEFAULT TECHNOLOGY BLOCK
-   *
-   *
-   *---------------------------------------------------------------------------------------------------
-   */
-  MEM_TECH_CONSTRUCTOR* CONST memTechInstalled[] = {    // Types of technology installed
-    NULL
-  };
-
-  /*---------------------------------------------------------------------------------------------------
-   * DEFAULT TECHNOLOGY MAP
-   *
-   *
-   *---------------------------------------------------------------------------------------------------
-   */
-  CONST UINT8 MemoryTechnologyMap[MAX_SOCKETS_SUPPORTED] = {0, 0, 0, 0, 0, 0, 0, 0};
-
-  /*---------------------------------------------------------------------------------------------------
-   * DEFAULT MAIN FEATURE BLOCK
-   *---------------------------------------------------------------------------------------------------
-   */
-  CONST MEM_FEAT_BLOCK_MAIN MemFeatMain = {
-    0
-  };
-
-  /*---------------------------------------------------------------------------------------------------
-   * DEFAULT NORTHBRIDGE SUPPORT LIST
-   *
-   *
-   *---------------------------------------------------------------------------------------------------
-   */
-  #if (OPTION_MEMCTLR_ON == TRUE)
-    #undef MEM_NB_SUPPORT_ON
-    #define MEM_NB_SUPPORT_ON { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_ON, MEM_IDENDIMM_ON },
-  #endif
-
-  /*---------------------------------------------------------------------------------------------------
-   * DEFAULT Technology Training
-   *
-   *
-   *---------------------------------------------------------------------------------------------------
-   */
-  #if OPTION_DDR3
-    CONST MEM_TECH_FEAT_BLOCK  memTechTrainingFeatDDR3 = {
-      0
-    };
-    CONST MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[] = {
-      { 0 }
-    };
-  #endif
-
-    /*---------------------------------------------------------------------------------------------------
-     * DEFAULT Platform Specific list
-     *
-     *
-     *---------------------------------------------------------------------------------------------------
-     */
-  #if (OPTION_MEMCTLR_ON == TRUE)
-    MEM_PLAT_SPEC_CFG* CONST memPlatSpecFFInstalledON[MAX_FF_TYPES] = {
-      NULL
-    };
-  #endif
-  /*----------------------------------------------------------------------
-   * DEFAULT PSCFG DEFINITIONS
-   *
-   *----------------------------------------------------------------------
-   */
-  MEM_PLATFORM_CFG* CONST memPlatformTypeInstalled[] = {
-    NULL
-  };
-
-  /*----------------------------------------------------------------------
-   * EXTRACTABLE PLATFORM SPECIFIC CONFIGURATION
-   *
-   *----------------------------------------------------------------------
-   */
-  MEM_PSC_FLOW_BLOCK* CONST memPlatSpecFlowArray[] = {
-    NULL
-  };
-
-  CONST MEM_TECH_LRDIMM memLrdimmSupported = {
-    MEM_TECH_LRDIMM_STRUCT_VERSION,
-    NULL
-  };
-#endif
-
-/*---------------------------------------------------------------------------------------------------
- * NORTHBRIDGE SUPPORT LIST
- *
- *
- *---------------------------------------------------------------------------------------------------
- */
-CONST MEM_NB_SUPPORT memNBInstalled[] = {
-  MEM_NB_SUPPORT_ON
-  MEM_NB_SUPPORT_END
-};
-
-#endif  // _OPTION_MEMORY_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f14/Config/OptionMsgBasedC1eInstall.h b/src/vendorcode/amd/agesa/f14/Config/OptionMsgBasedC1eInstall.h
deleted file mode 100644
index 3f9646c7af35..000000000000
--- a/src/vendorcode/amd/agesa/f14/Config/OptionMsgBasedC1eInstall.h
+++ /dev/null
@@ -1,71 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: Message-Based C1e
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Options
- * @e \$Revision: 34897 $   @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _OPTION_MSG_BASED_C1E_INSTALL_H_
-#define _OPTION_MSG_BASED_C1E_INSTALL_H_
-
-#include "cpuMsgBasedC1e.h"
-
-/*  This option is designed to be included into the platform solution install
- *  file. The platform solution install file will define the options status.
- *  Check to validate the definition
- */
-#define OPTION_MSG_BASED_C1E_FEAT
-#if OPTION_MSG_BASED_C1E == TRUE
-  #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE)
-
-    CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA MsgBasedC1eFamilyServiceArray[] =
-    {
-      {0, NULL}
-    };
-    CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA MsgBasedC1eFamilyServiceTable =
-    {
-      (sizeof (MsgBasedC1eFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
-      &MsgBasedC1eFamilyServiceArray[0]
-    };
-  #endif
-#endif
-#endif  // _OPTION_MSG_BASED_C1E_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f14/Config/OptionMultiSocketInstall.h b/src/vendorcode/amd/agesa/f14/Config/OptionMultiSocketInstall.h
deleted file mode 100644
index d6647254403b..000000000000
--- a/src/vendorcode/amd/agesa/f14/Config/OptionMultiSocketInstall.h
+++ /dev/null
@@ -1,92 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: Multiple Socket Support
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Options
- * @e \$Revision: 34897 $   @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _OPTION_MULTISOCKET_INSTALL_H_
-#define _OPTION_MULTISOCKET_INSTALL_H_
-
-/*  This option is designed to be included into the platform solution install
- *  file. The platform solution install file will define the options status.
- *  Check to validate the definition
- */
-#ifndef OPTION_MULTISOCKET
-  #error  BLDOPT: Option not defined: "OPTION_MULTISOCKET"
-#endif
-
-#if OPTION_MULTISOCKET == TRUE
-  OPTION_MULTISOCKET_PM_STEPS GetNumberOfSystemPmStepsPtrMulti;
-  #define GET_NUM_PM_STEPS    GetNumberOfSystemPmStepsPtrMulti
-  OPTION_MULTISOCKET_PM_CORE0_TASK RunCodeOnAllSystemCore0sMulti;
-  #define CORE0_PM_TASK       RunCodeOnAllSystemCore0sMulti
-  OPTION_MULTISOCKET_PM_NB_COF GetSystemNbCofMulti;
-  #define GET_SYS_NB_COF      GetSystemNbCofMulti
-  OPTION_MULTISOCKET_PM_NB_COF_UPDATE GetSystemNbCofVidUpdateMulti;
-  #define GET_SYS_NB_COF_UPDATE GetSystemNbCofVidUpdateMulti
-  OPTION_MULTISOCKET_PM_GET_EVENTS GetEarlyPmErrorsMulti;
-  #define GET_EARLY_PM_ERRORS GetEarlyPmErrorsMulti
-#else
-  OPTION_MULTISOCKET_PM_STEPS GetNumberOfSystemPmStepsPtrSingle;
-  #define GET_NUM_PM_STEPS    GetNumberOfSystemPmStepsPtrSingle
-  OPTION_MULTISOCKET_PM_CORE0_TASK RunCodeOnAllSystemCore0sSingle;
-  #define CORE0_PM_TASK       RunCodeOnAllSystemCore0sSingle
-  OPTION_MULTISOCKET_PM_NB_COF GetSystemNbCofSingle;
-  #define GET_SYS_NB_COF      GetSystemNbCofSingle
-  OPTION_MULTISOCKET_PM_NB_COF_UPDATE GetSystemNbCofVidUpdateSingle;
-  #define GET_SYS_NB_COF_UPDATE GetSystemNbCofVidUpdateSingle
-  OPTION_MULTISOCKET_PM_GET_EVENTS GetEarlyPmErrorsSingle;
-  #define GET_EARLY_PM_ERRORS GetEarlyPmErrorsSingle
-#endif
-
-/*  Declare the instance of the DMI option configuration structure  */
-CONST OPTION_MULTISOCKET_CONFIGURATION  OptionMultiSocketConfiguration = {
-  MULTISOCKET_STRUCT_VERSION,
-  GET_NUM_PM_STEPS,
-  CORE0_PM_TASK,
-  GET_SYS_NB_COF,
-  GET_SYS_NB_COF_UPDATE,
-  GET_EARLY_PM_ERRORS
-};
-
-#endif  // _OPTION_MULTISOCKET_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f14/Config/OptionPreserveMailboxInstall.h b/src/vendorcode/amd/agesa/f14/Config/OptionPreserveMailboxInstall.h
deleted file mode 100644
index f7979542b6b3..000000000000
--- a/src/vendorcode/amd/agesa/f14/Config/OptionPreserveMailboxInstall.h
+++ /dev/null
@@ -1,71 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: Preserve Mailbox
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Options
- * @e \$Revision: 34897 $   @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _OPTION_PRESERVE_MAILBOX_INSTALL_H_
-#define _OPTION_PRESERVE_MAILBOX_INSTALL_H_
-
-#include "PreserveMailbox.h"
-
-/*  This option is designed to be included into the platform solution install
- *  file. The platform solution install file will define the options status.
- *  Check to validate the definition
- */
-#define OPTION_PRESERVE_MAILBOX_FEAT
-
-#if ((AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE))
-
-  CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA PreserveMailboxFamilyServiceArray[] =
-  {
-    {0, NULL}
-  };
-  CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA PreserveMailboxFamilyServiceTable =
-  {
-    (sizeof (PreserveMailboxFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
-    &PreserveMailboxFamilyServiceArray[0]
-  };
-#endif
-
-#endif  // _OPTION_PRESERVE_MAILBOX_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f14/Config/OptionPstateInstall.h b/src/vendorcode/amd/agesa/f14/Config/OptionPstateInstall.h
deleted file mode 100644
index e7c0a1615f27..000000000000
--- a/src/vendorcode/amd/agesa/f14/Config/OptionPstateInstall.h
+++ /dev/null
@@ -1,215 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: PState
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Options
- * @e \$Revision: 34897 $   @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _OPTION_PSTATE_INSTALL_H_
-#define _OPTION_PSTATE_INSTALL_H_
-
-#include "cpuPstateTables.h"
-
-/*  This option is designed to be included into the platform solution install
- *  file. The platform solution install file will define the options status.
- *  Check to validate the definition
- */
-
-#define F14_PSTATE_SERVICE_SUPPORT
-
-#if ((AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE))
-  //
-  //Define Pstate CPU Family service
-  //
-
-  #ifdef OPTION_FAMILY14H
-    #if OPTION_FAMILY14H == TRUE
-      extern CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F14PstateServices;
-      #undef F14_PSTATE_SERVICE_SUPPORT
-      #define F14_PSTATE_SERVICE_SUPPORT {AMD_FAMILY_14, &F14PstateServices},
-    #endif
-  #endif
-
-  //
-  //Define ACPI Pstate objects.
-  //
-  #ifndef OPTION_ACPI_PSTATES
-    #error  BLDOPT: Option not defined: "OPTION_ACPI_PSTATES"
-  #endif
-  #if (OPTION_ACPI_PSTATES == TRUE)
-//    OPTION_SSDT_FEATURE               GenerateSsdt;
-    #define USER_SSDT_MAIN            GenerateSsdt
-    #ifndef OPTION_MULTISOCKET
-      #error  BLDOPT: Option not defined: "OPTION_MULTISOCKET"
-    #endif
-
-    OPTION_ACPI_FEATURE               CreatePStateAcpiTables;
-    OPTION_PSTATE_GATHER              PStateGatherMain;
-    #if ((OPTION_MULTISOCKET == TRUE) && (AGESA_ENTRY_INIT_POST == TRUE))
-      OPTION_PSTATE_LEVELING          PStateLevelingMain;
-      #define USER_PSTATE_OPTION_LEVEL  PStateLevelingMain
-    #else
-      OPTION_PSTATE_LEVELING            PStateLevelingStub;
-      #define USER_PSTATE_OPTION_LEVEL  PStateLevelingStub
-    #endif
-    #if AGESA_ENTRY_INIT_LATE == TRUE
-      #define USER_PSTATE_OPTION_MAIN   CreatePStateAcpiTables
-    #else
-      OPTION_ACPI_FEATURE               CreateAcpiTablesStub;
-      #define USER_PSTATE_OPTION_MAIN   CreateAcpiTablesStub
-    #endif
-    #if AGESA_ENTRY_INIT_POST == TRUE
-      #define USER_PSTATE_OPTION_GATHER PStateGatherMain
-    #else
-      OPTION_PSTATE_GATHER              PStateGatherStub;
-      #define USER_PSTATE_OPTION_GATHER PStateGatherStub
-    #endif
-    #if CFG_ACPI_PSTATES_PPC == TRUE
-      #define USER_PSTATE_CFG_PPC   TRUE
-    #else
-      #define USER_PSTATE_CFG_PPC   FALSE
-    #endif
-    #if CFG_ACPI_PSTATES_PCT == TRUE
-      #define USER_PSTATE_CFG_PCT   TRUE
-    #else
-      #define USER_PSTATE_CFG_PCT   FALSE
-    #endif
-    #if CFG_ACPI_PSTATES_PSD == TRUE
-      #define USER_PSTATE_CFG_PSD   TRUE
-    #else
-      #define USER_PSTATE_CFG_PSD   FALSE
-    #endif
-    #if CFG_ACPI_PSTATES_PSS == TRUE
-      #define USER_PSTATE_CFG_PSS   TRUE
-    #else
-      #define USER_PSTATE_CFG_PSS   FALSE
-    #endif
-    #if CFG_ACPI_PSTATES_XPSS == TRUE
-      #define USER_PSTATE_CFG_XPSS   TRUE
-    #else
-      #define USER_PSTATE_CFG_XPSS   FALSE
-    #endif
-
-    #if OPTION_IO_CSTATE == TRUE
-      OPTION_ACPI_FEATURE             CreateCStateAcpiTables;
-      #define USER_CSTATE_OPTION_MAIN CreateCStateAcpiTables
-    #else
-      OPTION_ACPI_FEATURE             CreateAcpiTablesStub;
-      #define USER_CSTATE_OPTION_MAIN CreateAcpiTablesStub
-    #endif
-  #else
-    OPTION_SSDT_FEATURE               GenerateSsdtStub;
-    OPTION_ACPI_FEATURE               CreateAcpiTablesStub;
-    OPTION_PSTATE_GATHER              PStateGatherStub;
-    OPTION_PSTATE_LEVELING            PStateLevelingStub;
-    #define USER_SSDT_MAIN            GenerateSsdtStub
-    #define USER_PSTATE_OPTION_MAIN   CreateAcpiTablesStub
-    #define USER_CSTATE_OPTION_MAIN   CreateAcpiTablesStub
-    #define USER_PSTATE_OPTION_GATHER PStateGatherStub
-    #define USER_PSTATE_OPTION_LEVEL  PStateLevelingStub
-    #define USER_PSTATE_CFG_PPC    FALSE
-    #define USER_PSTATE_CFG_PCT    FALSE
-    #define USER_PSTATE_CFG_PSD    FALSE
-    #define USER_PSTATE_CFG_PSS    FALSE
-    #define USER_PSTATE_CFG_XPSS   FALSE
-
-    // If ACPI Objects are disabled for PStates, we still need to check
-    // whether ACPI Objects are enabled for CStates
-    #if OPTION_IO_CSTATE == TRUE
-      OPTION_SSDT_FEATURE               GenerateSsdt;
-      OPTION_PSTATE_GATHER              PStateGatherMain;
-      OPTION_ACPI_FEATURE               CreateCStateAcpiTables;
-      #undef  USER_SSDT_MAIN
-      #define USER_SSDT_MAIN            GenerateSsdt
-      #undef  USER_PSTATE_OPTION_GATHER
-      #define USER_PSTATE_OPTION_GATHER PStateGatherMain
-      #undef  USER_CSTATE_OPTION_MAIN
-      #define USER_CSTATE_OPTION_MAIN   CreateCStateAcpiTables
-    #endif
-  #endif
-#else
-  OPTION_SSDT_FEATURE               GenerateSsdtStub;
-  OPTION_ACPI_FEATURE               CreateAcpiTablesStub;
-  OPTION_PSTATE_GATHER              PStateGatherStub;
-  OPTION_PSTATE_LEVELING            PStateLevelingStub;
-  #define USER_SSDT_MAIN            GenerateSsdtStub
-  #define USER_PSTATE_OPTION_MAIN   CreateAcpiTablesStub
-  #define USER_CSTATE_OPTION_MAIN   CreateAcpiTablesStub
-  #define USER_PSTATE_OPTION_GATHER PStateGatherStub
-  #define USER_PSTATE_OPTION_LEVEL  PStateLevelingStub
-  #define USER_PSTATE_CFG_PPC    FALSE
-  #define USER_PSTATE_CFG_PCT    FALSE
-  #define USER_PSTATE_CFG_PSD    FALSE
-  #define USER_PSTATE_CFG_PSS    FALSE
-  #define USER_PSTATE_CFG_XPSS   FALSE
-#endif
-
-/*  Declare the instance of the PSTATE option configuration structure  */
-CONST OPTION_PSTATE_POST_CONFIGURATION      OptionPstatePostConfiguration = {
-  PSTATE_STRUCT_VERSION,
-  USER_PSTATE_OPTION_GATHER,
-  USER_PSTATE_OPTION_LEVEL
-};
-
-CONST OPTION_PSTATE_LATE_CONFIGURATION      OptionPstateLateConfiguration = {
-  PSTATE_STRUCT_VERSION,
-  USER_SSDT_MAIN,
-  USER_PSTATE_OPTION_MAIN,
-  USER_CSTATE_OPTION_MAIN,
-  USER_PSTATE_CFG_PPC,
-  USER_PSTATE_CFG_PCT,
-  USER_PSTATE_CFG_PSD,
-  USER_PSTATE_CFG_PSS,
-  USER_PSTATE_CFG_XPSS
-};
-
-CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA PstateCpuFamilyServiceArray[] =
-{
-  F14_PSTATE_SERVICE_SUPPORT
-  {0, NULL}
-};
-CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA PstateFamilyServiceTable =
-{
-  (sizeof (PstateCpuFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
-  &PstateCpuFamilyServiceArray[0]
-};
-#endif  // _OPTION_PSTATE_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f14/Config/OptionS3ScriptInstall.h b/src/vendorcode/amd/agesa/f14/Config/OptionS3ScriptInstall.h
deleted file mode 100644
index 5b62bdf6dc15..000000000000
--- a/src/vendorcode/amd/agesa/f14/Config/OptionS3ScriptInstall.h
+++ /dev/null
@@ -1,91 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: S3SCRIPT
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Options
- * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
- */
-/*****************************************************************************
- *
- * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ***************************************************************************/
-
-#ifndef _OPTION_S3SCRIPT_INSTALL_H_
-#define _OPTION_S3SCRIPT_INSTALL_H_
-
-#include "S3SaveState.h"
-/*  This option is designed to be included into the platform solution install
- *  file. The platform solution install file will define the options status.
- *  Check to validate the definition
- */
-#ifndef OPTION_S3SCRIPT
-  #define OPTION_S3SCRIPT  FALSE    //if not define assume PI not use script
-#endif
-
-#if (AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_ENV == TRUE) || (AGESA_ENTRY_INIT_MID == TRUE)
-  #if OPTION_S3SCRIPT == TRUE
-    #define P_S3_SCRIPT_INIT      S3ScriptInitState
-  #endif
-#endif
-
-#if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE
-  #if OPTION_S3SCRIPT == TRUE
-    #define P_S3_SCRIPT_RESTORE   S3ScriptRestoreState
-  #endif
-#endif
-
-#ifndef P_S3_SCRIPT_INIT
-  #define P_S3_SCRIPT_INIT        S3ScriptInitStateStub
-#endif
-
-#ifndef P_S3_SCRIPT_RESTORE
-  #define P_S3_SCRIPT_RESTORE     S3ScriptInitStateStub
-  #undef  GNB_S3_DISPATCH_FUNCTION_TABLE
-#endif
-
-#ifndef GNB_S3_DISPATCH_FUNCTION_TABLE
-  #define GNB_S3_DISPATCH_FUNCTION_TABLE
-#endif
-
-/*  Declare the instance of the S3SCRIPT option configuration structure  */
-S3_SCRIPT_CONFIGURATION OptionS3ScriptConfiguration = {
-  P_S3_SCRIPT_INIT,
-  P_S3_SCRIPT_RESTORE
-};
-
-S3_DISPATCH_FUNCTION_ENTRY S3DispatchFunctionTable [] = {
-  GNB_S3_DISPATCH_FUNCTION_TABLE
-  {0, NULL}
-};
-#endif  // _OPTION_S3SCRIPT_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f14/Config/OptionSlitInstall.h b/src/vendorcode/amd/agesa/f14/Config/OptionSlitInstall.h
deleted file mode 100644
index 915e5302c4bf..000000000000
--- a/src/vendorcode/amd/agesa/f14/Config/OptionSlitInstall.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: SLIT
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Options
- * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
- */
-/*****************************************************************************
- *
- * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ***************************************************************************/
-
-#ifndef _OPTION_SLIT_INSTALL_H_
-#define _OPTION_SLIT_INSTALL_H_
-
-/*  This option is designed to be included into the platform solution install
- *  file. The platform solution install file will define the options status.
- *  Check to validate the definition
- */
-#if AGESA_ENTRY_INIT_LATE == TRUE
-  #ifndef OPTION_SLIT
-    #error  BLDOPT: Option not defined: "OPTION_SLIT"
-  #endif
-  #if OPTION_SLIT == TRUE
-    OPTION_SLIT_FEATURE               GetAcpiSlitMain;
-    OPTION_SLIT_RELEASE_BUFFER   ReleaseSlitBuffer;
-    #define USER_SLIT_OPTION     GetAcpiSlitMain
-    #define USER_SLIT_RELEASE_BUFFER ReleaseSlitBuffer
-  #else
-    OPTION_SLIT_FEATURE               GetAcpiSlitStub;
-    OPTION_SLIT_RELEASE_BUFFER   ReleaseSlitBufferStub;
-    #define USER_SLIT_OPTION     GetAcpiSlitStub
-    #define USER_SLIT_RELEASE_BUFFER ReleaseSlitBufferStub
-  #endif
-#else
-  OPTION_SLIT_FEATURE               GetAcpiSlitStub;
-  OPTION_SLIT_RELEASE_BUFFER   ReleaseSlitBufferStub;
-  #define USER_SLIT_OPTION     GetAcpiSlitStub
-  #define USER_SLIT_RELEASE_BUFFER ReleaseSlitBufferStub
-#endif
-/*  Declare the instance of the SLIT option configuration structure  */
-OPTION_SLIT_CONFIGURATION OptionSlitConfiguration = {
-  SLIT_STRUCT_VERSION,
-  USER_SLIT_OPTION,
-  USER_SLIT_RELEASE_BUFFER
-};
-
-#endif  // _OPTION_SLIT_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f14/Config/OptionSratInstall.h b/src/vendorcode/amd/agesa/f14/Config/OptionSratInstall.h
deleted file mode 100644
index 273874753f3e..000000000000
--- a/src/vendorcode/amd/agesa/f14/Config/OptionSratInstall.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: SRAT
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Options
- * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
- */
-/*****************************************************************************
- *
- * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ***************************************************************************/
-
-#ifndef _OPTION_SRAT_INSTALL_H_
-#define _OPTION_SRAT_INSTALL_H_
-
-/*  This option is designed to be included into the platform solution install
- *  file. The platform solution install file will define the options status.
- *  Check to validate the definition
- */
-#if AGESA_ENTRY_INIT_LATE == TRUE
-  #ifndef OPTION_SRAT
-    #error  BLDOPT: Option not defined: "OPTION_SRAT"
-  #endif
-  #if OPTION_SRAT == TRUE
-    OPTION_SRAT_FEATURE          GetAcpiSratMain;
-    #define USER_SRAT_OPTION     GetAcpiSratMain
-  #else
-    OPTION_SRAT_FEATURE          GetAcpiSratStub;
-    #define USER_SRAT_OPTION     GetAcpiSratStub
-  #endif
-#else
-  OPTION_SRAT_FEATURE            GetAcpiSratStub;
-  #define USER_SRAT_OPTION       GetAcpiSratStub
-#endif
-
-/*  Declare the instance of the WHEA option configuration structure  */
-OPTION_SRAT_CONFIGURATION OptionSratConfiguration = {
-  SRAT_STRUCT_VERSION,
-  USER_SRAT_OPTION
-};
-
-#endif  // _OPTION_WHEA_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f14/Config/OptionSwC1eInstall.h b/src/vendorcode/amd/agesa/f14/Config/OptionSwC1eInstall.h
deleted file mode 100644
index 4e4b55f3c556..000000000000
--- a/src/vendorcode/amd/agesa/f14/Config/OptionSwC1eInstall.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: SW C1e
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Options
- * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
- */
-/*****************************************************************************
- *
- * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ***************************************************************************/
-
-#ifndef _OPTION_SW_C1E_INSTALL_H_
-#define _OPTION_SW_C1E_INSTALL_H_
-
-#include "cpuSwC1e.h"
-
-/*  This option is designed to be included into the platform solution install
- *  file. The platform solution install file will define the options status.
- *  Check to validate the definition
- */
-#define OPTION_SW_C1E_FEAT
-#if AGESA_ENTRY_INIT_EARLY == TRUE
-  CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA SwC1eFamilyServiceArray[] =
-  {
-    {0, NULL}
-  };
-  CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA SwC1eFamilyServiceTable =
-  {
-    (sizeof (SwC1eFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
-    &SwC1eFamilyServiceArray[0]
-  };
-#endif
-
-#endif  // _OPTION_SW_C1E_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f14/Config/OptionWheaInstall.h b/src/vendorcode/amd/agesa/f14/Config/OptionWheaInstall.h
deleted file mode 100644
index 5facece353a2..000000000000
--- a/src/vendorcode/amd/agesa/f14/Config/OptionWheaInstall.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: WHEA
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Options
- * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
- */
-/*****************************************************************************
- *
- * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ***************************************************************************/
-
-#ifndef _OPTION_WHEA_INSTALL_H_
-#define _OPTION_WHEA_INSTALL_H_
-
-/*  This option is designed to be included into the platform solution install
- *  file. The platform solution install file will define the options status.
- *  Check to validate the definition
- */
-#if AGESA_ENTRY_INIT_LATE == TRUE
-  #ifndef OPTION_WHEA
-    #error  BLDOPT: Option not defined: "OPTION_WHEA"
-  #endif
-  #if OPTION_WHEA == TRUE
-    OPTION_WHEA_FEATURE          GetAcpiWheaMain;
-    #define USER_WHEA_OPTION     GetAcpiWheaMain
-  #else
-    OPTION_WHEA_FEATURE          GetAcpiWheaStub;
-    #define USER_WHEA_OPTION     GetAcpiWheaStub
-  #endif
-
-#else
-  OPTION_WHEA_FEATURE            GetAcpiWheaStub;
-  #define USER_WHEA_OPTION       GetAcpiWheaStub
-#endif
-
-/*  Declare the instance of the WHEA option configuration structure  */
-OPTION_WHEA_CONFIGURATION OptionWheaConfiguration = {
-  WHEA_STRUCT_VERSION,
-  USER_WHEA_OPTION
-};
-
-#endif  // _OPTION_WHEA_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h b/src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h
deleted file mode 100644
index 53b2d61d9330..000000000000
--- a/src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h
+++ /dev/null
@@ -1,1584 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build options for a combination of package type, processor, and features.
- *
- * This file generates the defaults tables for the all platform solution
- * combinations.  The documented build options are imported from a user
- * controlled file for processing.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Core
- * @e \$Revision: 47417 $   @e \$Date: 2011-02-18 12:48:20 -0700 (Fri, 18 Feb 2011) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*****************************************************************************
- *
- * Start processing the user options:  First, set default settings
- *
- ****************************************************************************/
-
-CONST AMD_MODULE_HEADER mCpuModuleID = {
-  //ModuleHeaderSignature
-  // Remove 'DOM$' as temp solution before update BinUtil.exe ,
-  Int32FromChar ('0', '0', '0', '0'),
-  //ModuleIdentifier[8]
-  AGESA_ID,
-  //ModuleVersion[12]
-  AGESA_VERSION_STRING,
-  //ModuleDispatcher
-  NULL,//(VOID *)(UINT64)((MODULE_ENTRY)AmdAgesaDispatcher),
-  //NextBlock
-  NULL
-};
-
-/* The default fixed MTRR values to be set after memory initialization */
-static const AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
-{
-	{ AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull },
-	{ AMD_AP_MTRR_FIX4k_C0000,  0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_C8000,  0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_D0000,  0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_D8000,  0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_E0000,  0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_E8000,  0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_F0000,  0x1E1E1E1E1E1E1E1Eull },
-	{ AMD_AP_MTRR_FIX4k_F8000,  0x1E1E1E1E1E1E1E1Eull },
-	{ CPU_LIST_TERMINAL },
-};
-
-/* Process solution defined socket / family installations
- *
- * As part of the release package for each image, define the options below to select the
- * AGESA processor support included in that image.
- */
-
-/*  Default sockets to off  */
-#define OPTION_FT1_SOCKET_SUPPORT    FALSE
-
-/*  Default families to off  */
-#define OPTION_FAMILY14H             FALSE
-
-/*  Enable the appropriate socket support  */
-#ifdef INSTALL_FT1_SOCKET_SUPPORT
-  #if  INSTALL_FT1_SOCKET_SUPPORT == TRUE
-    #undef OPTION_FT1_SOCKET_SUPPORT
-    #define OPTION_FT1_SOCKET_SUPPORT  TRUE
-  #endif
-#endif
-
-// F14 is supported in FT1
-#ifdef INSTALL_FAMILY_14_SUPPORT
-  #if  INSTALL_FAMILY_14_SUPPORT == TRUE
-    #undef OPTION_FAMILY14H
-    #define OPTION_FAMILY14H     TRUE
-  #endif
-#endif
-
-#if (OPTION_FAMILY14H == TRUE)
-  #if (OPTION_FT1_SOCKET_SUPPORT == FALSE)
-    #undef OPTION_FAMILY14H
-    #define OPTION_FAMILY14H  FALSE
-  #endif
-#endif
-
-
-/*  Check for invalid combinations of socket/family */
-
-#if (OPTION_FT1_SOCKET_SUPPORT == TRUE)
-  #if (OPTION_FAMILY14H == FALSE)
-    #error No FT1 supported families included in the build
-  #endif
-#endif
-
-/* Process AGESA private data
- *
- * Turn on appropriate CPU models and memory controllers,
- * as well as some other memory controls.
- */
-
-/*  Default all models to off  */
-#define OPTION_FAMILY14H_ON          FALSE
-
-/*  Default all memory controllers to off  */
-#define OPTION_MEMCTLR_ON            FALSE
-
-/*  Default all memory controls to off  */
-#define OPTION_HW_WRITE_LEV_TRAINING            FALSE
-#define OPTION_SW_WRITE_LEV_TRAINING            FALSE
-#define OPTION_CONTINOUS_PATTERN_GENERATION     FALSE
-#define OPTION_HW_DQS_REC_EN_TRAINING           FALSE
-#define OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING   FALSE
-#define OPTION_OPT_SW_DQS_REC_EN_TRAINING       FALSE
-#define OPTION_NON_OPT_SW_RD_WR_POS_TRAINING    FALSE
-#define OPTION_OPT_SW_RD_WR_POS_TRAINING        FALSE
-#define OPTION_MAX_RD_LAT_TRAINING              FALSE
-#define OPTION_HW_DRAM_INIT                     FALSE
-#define OPTION_SW_DRAM_INIT                     FALSE
-#define OPTION_S3_MEM_SUPPORT                   FALSE
-#define OPTION_ADDR_TO_CS_TRANSLATOR            FALSE
-
-/*  Defaults for public user options  */
-#define OPTION_UDIMMS                           FALSE
-#define OPTION_RDIMMS                           FALSE
-#define OPTION_SODIMMS                          FALSE
-#define OPTION_LRDIMMS                          FALSE
-#define OPTION_DDR3                             FALSE
-#define OPTION_ECC                              FALSE
-#define OPTION_BANK_INTERLEAVE                  FALSE
-#define OPTION_DCT_INTERLEAVE                   FALSE
-#define OPTION_NODE_INTERLEAVE                  FALSE
-#define OPTION_PARALLEL_TRAINING                FALSE
-#define OPTION_ONLINE_SPARE                     FALSE
-#define OPTION_MEM_RESTORE                      FALSE
-#define OPTION_DIMM_EXCLUDE                     FALSE
-
-/*  Default all CPU controls to off  */
-#define OPTION_MULTISOCKET                      FALSE
-#define OPTION_SRAT                             FALSE
-#define OPTION_SLIT                             FALSE
-#define OPTION_HT_ASSIST                        FALSE
-#define OPTION_ATM_MODE                         FALSE
-#define OPTION_CPU_CORELEVLING                  FALSE
-#define OPTION_MSG_BASED_C1E                    FALSE
-#define OPTION_CPU_CFOH                         FALSE
-#define OPTION_C6_STATE                         FALSE
-#define OPTION_IO_CSTATE                        FALSE
-#define OPTION_CPB                              FALSE
-#define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT   FALSE
-#define OPTION_S3SCRIPT                         FALSE
-#define OPTION_GFX_RECOVERY                     FALSE
-
-/*  Enable all private controls based on socket/family enables  */
-
-#if (OPTION_FT1_SOCKET_SUPPORT == TRUE)
-  #if (OPTION_FAMILY14H == TRUE)
-    #undef OPTION_FAMILY14H_ON
-    #define OPTION_FAMILY14H_ON  TRUE
-    #undef OPTION_MEMCTLR_ON
-    #define OPTION_MEMCTLR_ON    TRUE
-    #undef OPTION_HW_WRITE_LEV_TRAINING
-    #define OPTION_HW_WRITE_LEV_TRAINING  TRUE
-    #undef OPTION_CONTINOUS_PATTERN_GENERATION
-    #define OPTION_CONTINOUS_PATTERN_GENERATION  TRUE
-    #undef OPTION_MAX_RD_LAT_TRAINING
-    #define OPTION_MAX_RD_LAT_TRAINING  TRUE
-    #undef OPTION_HW_DQS_REC_EN_TRAINING
-    #define OPTION_HW_DQS_REC_EN_TRAINING  TRUE
-    #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
-    #define OPTION_OPT_SW_RD_WR_POS_TRAINING  TRUE
-    #undef OPTION_SW_DRAM_INIT
-    #define OPTION_SW_DRAM_INIT  TRUE
-    #undef OPTION_S3_MEM_SUPPORT
-    #define OPTION_S3_MEM_SUPPORT  TRUE
-    #undef OPTION_C6_STATE
-    #define OPTION_C6_STATE  TRUE
-    #undef OPTION_CPB
-    #define OPTION_CPB TRUE
-    #undef OPTION_IO_CSTATE
-    #define OPTION_IO_CSTATE TRUE
-    #undef OPTION_S3SCRIPT
-    #define OPTION_S3SCRIPT  TRUE
-    #undef OPTION_UDIMMS
-    #define OPTION_UDIMMS  TRUE
-    #undef OPTION_SODIMMS
-    #define OPTION_SODIMMS  TRUE
-    #undef OPTION_DDR3
-    #define OPTION_DDR3  TRUE
-    #undef OPTION_BANK_INTERLEAVE
-    #define OPTION_BANK_INTERLEAVE  TRUE
-    #undef OPTION_MEM_RESTORE
-    #define OPTION_MEM_RESTORE  TRUE
-    #undef OPTION_DIMM_EXCLUDE
-    #define OPTION_DIMM_EXCLUDE  TRUE
-  #endif
-#endif
-
-#if (OPTION_FAMILY14H == TRUE)
-  #undef  GNB_SUPPORT
-  #define GNB_SUPPORT   TRUE
-#endif
-
-#define OPTION_ACPI_PSTATES             TRUE
-#define OPTION_WHEA                     TRUE
-#define OPTION_DMI                      FALSE
-#define OPTION_EARLY_SAMPLES            FALSE
-#define CFG_ACPI_PSTATES_PPC            TRUE
-#define CFG_ACPI_PSTATES_PCT            TRUE
-#define CFG_ACPI_PSTATES_PSD            TRUE
-#define CFG_ACPI_PSTATES_PSS            TRUE
-#define CFG_ACPI_PSTATES_XPSS           TRUE
-#define CFG_ACPI_PSTATE_PSD_INDPX       FALSE
-#define CFG_VRM_HIGH_SPEED_ENABLE       TRUE
-#define CFG_VRM_NB_HIGH_SPEED_ENABLE    FALSE
-#define OPTION_ALIB                     TRUE
-/*---------------------------------------------------------------------------
- *       Processing the options:  Second, process the user's selections
- *--------------------------------------------------------------------------*/
-#ifdef BLDOPT_REMOVE_MULTISOCKET_SUPPORT
-  #if  BLDOPT_REMOVE_MULTISOCKET_SUPPORT == TRUE
-    #undef  OPTION_MULTISOCKET
-    #define OPTION_MULTISOCKET          FALSE
-  #endif
-#endif
-#ifdef BLDOPT_REMOVE_ECC_SUPPORT
-  #if  BLDOPT_REMOVE_ECC_SUPPORT == TRUE
-    #undef  OPTION_ECC
-    #define OPTION_ECC        FALSE
-  #endif
-#endif
-#ifdef BLDOPT_REMOVE_UDIMMS_SUPPORT
-  #if  BLDOPT_REMOVE_UDIMMS_SUPPORT == TRUE
-    #undef  OPTION_UDIMMS
-    #define OPTION_UDIMMS               FALSE
-  #endif
-#endif
-#ifdef BLDOPT_REMOVE_RDIMMS_SUPPORT
-  #if  BLDOPT_REMOVE_RDIMMS_SUPPORT == TRUE
-    #undef  OPTION_RDIMMS
-    #define OPTION_RDIMMS               FALSE
-  #endif
-#endif
-#ifdef BLDOPT_REMOVE_SODIMMS_SUPPORT
-  #if  BLDOPT_REMOVE_SODIMMS_SUPPORT == TRUE
-    #undef  OPTION_SODIMMS
-    #define OPTION_SODIMMS               FALSE
-  #endif
-#endif
-#ifdef BLDOPT_REMOVE_LRDIMMS_SUPPORT
-  #if  BLDOPT_REMOVE_LRDIMMS_SUPPORT == TRUE
-    #undef  OPTION_LRDIMMS
-    #define OPTION_LRDIMMS               FALSE
-  #endif
-#endif
-#ifdef BLDOPT_REMOVE_BANK_INTERLEAVE
-  #if  BLDOPT_REMOVE_BANK_INTERLEAVE == TRUE
-    #undef  OPTION_BANK_INTERLEAVE
-    #define OPTION_BANK_INTERLEAVE      FALSE
-  #endif
-#endif
-#ifdef BLDOPT_REMOVE_DCT_INTERLEAVE
-  #if  BLDOPT_REMOVE_DCT_INTERLEAVE == TRUE
-    #undef  OPTION_DCT_INTERLEAVE
-    #define OPTION_DCT_INTERLEAVE       FALSE
-  #endif
-#endif
-#ifdef BLDOPT_REMOVE_NODE_INTERLEAVE
-  #if  BLDOPT_REMOVE_NODE_INTERLEAVE == TRUE
-    #undef  OPTION_NODE_INTERLEAVE
-    #define OPTION_NODE_INTERLEAVE      FALSE
-  #endif
-#endif
-#ifdef BLDOPT_REMOVE_PARALLEL_TRAINING
-  #if  BLDOPT_REMOVE_PARALLEL_TRAINING == TRUE
-    #undef  OPTION_PARALLEL_TRAINING
-    #define OPTION_PARALLEL_TRAINING    FALSE
-  #endif
-#endif
-/* Originally BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT, but inverted alongside the default value */
-#ifdef BLDOPT_ENABLE_ONLINE_SPARE_SUPPORT
-  #if  BLDOPT_ENABLE_ONLINE_SPARE_SUPPORT == TRUE
-    #undef  OPTION_ONLINE_SPARE
-    #define OPTION_ONLINE_SPARE         TRUE
-  #endif
-#endif
-#ifdef BLDOPT_REMOVE_MEM_RESTORE_SUPPORT
-  #if  BLDOPT_REMOVE_MEM_RESTORE_SUPPORT == TRUE
-    #undef  OPTION_MEM_RESTORE
-    #define OPTION_MEM_RESTORE         FALSE
-  #endif
-#endif
-#ifdef BLDOPT_REMOVE_ACPI_PSTATES
-  #if  BLDOPT_REMOVE_ACPI_PSTATES == TRUE
-    #undef  OPTION_ACPI_PSTATES
-    #define OPTION_ACPI_PSTATES         FALSE
-  #endif
-#endif
-#ifdef BLDOPT_REMOVE_SRAT
-  #if  BLDOPT_REMOVE_SRAT == TRUE
-    #undef  OPTION_SRAT
-    #define OPTION_SRAT                 FALSE
-  #endif
-#endif
-#ifdef BLDOPT_REMOVE_SLIT
-  #if  BLDOPT_REMOVE_SLIT == TRUE
-    #undef  OPTION_SLIT
-    #define OPTION_SLIT                 FALSE
-  #endif
-#endif
-#ifdef BLDOPT_REMOVE_WHEA
-  #if  BLDOPT_REMOVE_WHEA == TRUE
-    #undef  OPTION_WHEA
-    #define OPTION_WHEA                 FALSE
-  #endif
-#endif
-/* Originally BLDOPT_REMOVE_DMI, but inverted alongside the default value */
-#ifdef BLDOPT_ENABLE_DMI
-  #if  BLDOPT_ENABLE_DMI == TRUE
-    #undef  OPTION_DMI
-    #define OPTION_DMI                  TRUE
-  #endif
-#endif
-#ifdef BLDOPT_REMOVE_ADDR_TO_CS_TRANSLATOR
-  #if  BLDOPT_REMOVE_ADDR_TO_CS_TRANSLATOR == TRUE
-    #undef  OPTION_ADDR_TO_CS_TRANSLATOR
-    #define OPTION_ADDR_TO_CS_TRANSLATOR        FALSE
-  #endif
-#endif
-
-#ifdef BLDOPT_REMOVE_HT_ASSIST
-  #if  BLDOPT_REMOVE_HT_ASSIST == TRUE
-    #undef  OPTION_HT_ASSIST
-    #define OPTION_HT_ASSIST      FALSE
-  #endif
-#endif
-
-#ifdef BLDOPT_REMOVE_ATM_MODE
-  #if  BLDOPT_REMOVE_ATM_MODE == TRUE
-    #undef  OPTION_ATM_MODE
-    #define OPTION_ATM_MODE      FALSE
-  #endif
-#endif
-
-#ifdef BLDOPT_REMOVE_MSG_BASED_C1E
-  #if  BLDOPT_REMOVE_MSG_BASED_C1E == TRUE
-    #undef  OPTION_MSG_BASED_C1E
-    #define OPTION_MSG_BASED_C1E      FALSE
-  #endif
-#endif
-
-#ifdef BLDOPT_REMOVE_C6_STATE
-  #if  BLDOPT_REMOVE_C6_STATE == TRUE
-    #undef  OPTION_C6_STATE
-    #define OPTION_C6_STATE      FALSE
-  #endif
-#endif
-
-/* Originally BLDOPT_REMOVE_GFX_RECOVERY, but inverted alongside the default value */
-#ifdef BLDOPT_ENABLE_GFX_RECOVERY
-  #if  BLDOPT_ENABLE_GFX_RECOVERY == TRUE
-    #undef  OPTION_GFX_RECOVERY
-    #define OPTION_GFX_RECOVERY         TRUE
-  #endif
-#endif
-
-#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PPC
-  #if  BLDCFG_REMOVE_ACPI_PSTATES_PPC == TRUE
-    #undef  CFG_ACPI_PSTATES_PPC
-    #define CFG_ACPI_PSTATES_PPC        FALSE
-  #endif
-#endif
-
-#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PCT
-  #if  BLDCFG_REMOVE_ACPI_PSTATES_PCT == TRUE
-    #undef  CFG_ACPI_PSTATES_PCT
-    #define CFG_ACPI_PSTATES_PCT        FALSE
-  #endif
-#endif
-
-#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PSD
-  #if  BLDCFG_REMOVE_ACPI_PSTATES_PSD == TRUE
-    #undef  CFG_ACPI_PSTATES_PSD
-    #define CFG_ACPI_PSTATES_PSD        FALSE
-  #endif
-#endif
-
-#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PSS
-  #if  BLDCFG_REMOVE_ACPI_PSTATES_PSS == TRUE
-    #undef  CFG_ACPI_PSTATES_PSS
-    #define CFG_ACPI_PSTATES_PSS        FALSE
-  #endif
-#endif
-
-#ifdef BLDCFG_REMOVE_ACPI_PSTATES_XPSS
-  #if  BLDCFG_REMOVE_ACPI_PSTATES_XPSS == TRUE
-    #undef  CFG_ACPI_PSTATES_XPSS
-    #define CFG_ACPI_PSTATES_XPSS       FALSE
-  #endif
-#endif
-
-#ifdef BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT
-  #if  BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT == TRUE
-    #undef  CFG_ACPI_PSTATE_PSD_INDPX
-    #define CFG_ACPI_PSTATE_PSD_INDPX       TRUE
-  #endif
-#endif
-
-/* Originally BLDCFG_VRM_HIGH_SPEED_ENABLE, but inverted alongside the default value */
-#ifdef BLDCFG_VRM_HIGH_SPEED_DISABLE
-  #if  BLDCFG_VRM_HIGH_SPEED_DISABLE == TRUE
-    #undef  CFG_VRM_HIGH_SPEED_ENABLE
-    #define CFG_VRM_HIGH_SPEED_ENABLE       FALSE
-  #endif
-#endif
-
-#ifdef BLDCFG_VRM_NB_HIGH_SPEED_ENABLE
-  #if BLDCFG_VRM_NB_HIGH_SPEED_ENABLE == TRUE
-    #undef CFG_VRM_NB_HIGH_SPEED_ENABLE
-    #define CFG_VRM_NB_HIGH_SPEED_ENABLE    TRUE
-  #endif
-#endif
-
-#ifdef BLDCFG_STARTING_BUSNUM
-  #define CFG_STARTING_BUSNUM         (BLDCFG_STARTING_BUSNUM)
-#else
-  #define CFG_STARTING_BUSNUM         (0)
-#endif
-
-#ifdef BLDCFG_AMD_PLATFORM_TYPE
-  #define CFG_AMD_PLATFORM_TYPE              BLDCFG_AMD_PLATFORM_TYPE
-#else
-  #define CFG_AMD_PLATFORM_TYPE              0
-#endif
-
-CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
-
-#ifdef BLDCFG_MAXIMUM_BUSNUM
-  #define CFG_MAXIMUM_BUSNUM          (BLDCFG_MAXIMUM_BUSNUM)
-#else
-  #define CFG_MAXIMUM_BUSNUM          (0xF8)
-#endif
-
-#ifdef BLDCFG_ALLOCATED_BUSNUM
-  #define CFG_ALLOCATED_BUSNUM        (BLDCFG_ALLOCATED_BUSNUM)
-#else
-  #define CFG_ALLOCATED_BUSNUM        (0x20)
-#endif
-
-#ifdef BLDCFG_BUID_SWAP_LIST
-  #define CFG_BUID_SWAP_LIST         (BLDCFG_BUID_SWAP_LIST)
-#else
-  #define CFG_BUID_SWAP_LIST         (NULL)
-#endif
-
-#ifdef BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST
-  #define CFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST         (BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST)
-#else
-  #define CFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST         (NULL)
-#endif
-
-#ifdef BLDCFG_HTFABRIC_LIMITS_LIST
-  #define CFG_HTFABRIC_LIMITS_LIST         (BLDCFG_HTFABRIC_LIMITS_LIST)
-#else
-  #define CFG_HTFABRIC_LIMITS_LIST         (NULL)
-#endif
-
-#ifdef BLDCFG_HTCHAIN_LIMITS_LIST
-  #define CFG_HTCHAIN_LIMITS_LIST         (BLDCFG_HTCHAIN_LIMITS_LIST)
-#else
-  #define CFG_HTCHAIN_LIMITS_LIST         (NULL)
-#endif
-
-#ifdef BLDCFG_BUS_NUMBERS_LIST
-  #define CFG_BUS_NUMBERS_LIST         (BLDCFG_BUS_NUMBERS_LIST)
-#else
-  #define CFG_BUS_NUMBERS_LIST         (NULL)
-#endif
-
-#ifdef BLDCFG_IGNORE_LINK_LIST
-  #define CFG_IGNORE_LINK_LIST         (BLDCFG_IGNORE_LINK_LIST)
-#else
-  #define CFG_IGNORE_LINK_LIST         (NULL)
-#endif
-
-#ifdef BLDCFG_LINK_SKIP_REGANG_LIST
-  #define CFG_LINK_SKIP_REGANG_LIST         (BLDCFG_LINK_SKIP_REGANG_LIST)
-#else
-  #define CFG_LINK_SKIP_REGANG_LIST         (NULL)
-#endif
-
-#ifdef BLDCFG_SET_HTCRC_SYNC_FLOOD
-  #define CFG_SET_HTCRC_SYNC_FLOOD         (BLDCFG_SET_HTCRC_SYNC_FLOOD)
-#else
-  #define CFG_SET_HTCRC_SYNC_FLOOD         (FALSE)
-#endif
-
-#ifdef BLDCFG_USE_UNIT_ID_CLUMPING
-  #define CFG_USE_UNIT_ID_CLUMPING         (BLDCFG_USE_UNIT_ID_CLUMPING)
-#else
-  #define CFG_USE_UNIT_ID_CLUMPING         (FALSE)
-#endif
-
-#ifdef BLDCFG_ADDITIONAL_TOPOLOGIES_LIST
-  #define CFG_ADDITIONAL_TOPOLOGIES_LIST         (BLDCFG_ADDITIONAL_TOPOLOGIES_LIST)
-#else
-  #define CFG_ADDITIONAL_TOPOLOGIES_LIST         (NULL)
-#endif
-
-#ifdef BLDCFG_USE_HT_ASSIST
-  #define CFG_USE_HT_ASSIST               (BLDCFG_USE_HT_ASSIST)
-#else
-  #define CFG_USE_HT_ASSIST               (TRUE)
-#endif
-
-#ifdef BLDCFG_USE_ATM_MODE
-  #define CFG_USE_ATM_MODE                (BLDCFG_USE_ATM_MODE)
-#else
-  #define CFG_USE_ATM_MODE                (TRUE)
-#endif
-
-#ifdef BLDCFG_PLATFORM_CONTROL_FLOW_MODE
-  #define CFG_PLATFORM_CONTROL_FLOW_MODE  (BLDCFG_PLATFORM_CONTROL_FLOW_MODE)
-#else
-  #define CFG_PLATFORM_CONTROL_FLOW_MODE  (Nfcm)
-#endif
-
-#ifdef BLDCFG_PLATFORM_DEEMPHASIS_LIST
-  #define CFG_PLATFORM_DEEMPHASIS_LIST  (BLDCFG_PLATFORM_DEEMPHASIS_LIST)
-#else
-  #define CFG_PLATFORM_DEEMPHASIS_LIST  (NULL)
-#endif
-
-#ifdef BLDCFG_VRM_ADDITIONAL_DELAY
-  #define CFG_VRM_ADDITIONAL_DELAY      (BLDCFG_VRM_ADDITIONAL_DELAY)
-#else
-  #define CFG_VRM_ADDITIONAL_DELAY      (0)
-#endif
-
-#ifdef BLDCFG_VRM_CURRENT_LIMIT
-  #define CFG_VRM_CURRENT_LIMIT            BLDCFG_VRM_CURRENT_LIMIT
-#else
-  #define CFG_VRM_CURRENT_LIMIT            24000
-#endif
-
-#ifdef BLDCFG_VRM_LOW_POWER_THRESHOLD
-  #define CFG_VRM_LOW_POWER_THRESHOLD      BLDCFG_VRM_LOW_POWER_THRESHOLD
-#else
-  #define CFG_VRM_LOW_POWER_THRESHOLD      24000
-#endif
-
-#ifdef BLDCFG_VRM_SLEW_RATE
-  #define CFG_VRM_SLEW_RATE                BLDCFG_VRM_SLEW_RATE
-#else
-  #define CFG_VRM_SLEW_RATE                (5000)
-#endif
-
-#ifdef BLDCFG_VRM_INRUSH_CURRENT_LIMIT
-  #define CFG_VRM_INRUSH_CURRENT_LIMIT     BLDCFG_VRM_INRUSH_CURRENT_LIMIT
-#else
-  #define CFG_VRM_INRUSH_CURRENT_LIMIT     (6000)
-#endif
-
-#ifdef BLDCFG_VRM_NB_ADDITIONAL_DELAY
-  #define CFG_VRM_NB_ADDITIONAL_DELAY      (BLDCFG_VRM_NB_ADDITIONAL_DELAY)
-#else
-  #define CFG_VRM_NB_ADDITIONAL_DELAY      (0)
-#endif
-
-#ifdef BLDCFG_VRM_NB_CURRENT_LIMIT
-  #define CFG_VRM_NB_CURRENT_LIMIT         BLDCFG_VRM_NB_CURRENT_LIMIT
-#else
-  #define CFG_VRM_NB_CURRENT_LIMIT         (0)
-#endif
-
-#ifdef BLDCFG_VRM_NB_LOW_POWER_THRESHOLD
-  #define CFG_VRM_NB_LOW_POWER_THRESHOLD   BLDCFG_VRM_NB_LOW_POWER_THRESHOLD
-#else
-  #define CFG_VRM_NB_LOW_POWER_THRESHOLD   (0)
-#endif
-
-#ifdef BLDCFG_VRM_NB_SLEW_RATE
-  #define CFG_VRM_NB_SLEW_RATE             BLDCFG_VRM_NB_SLEW_RATE
-#else
-  #define CFG_VRM_NB_SLEW_RATE             (5000)
-#endif
-
-#ifdef BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT
-  #define CFG_VRM_NB_INRUSH_CURRENT_LIMIT  BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT
-#else
-  #define CFG_VRM_NB_INRUSH_CURRENT_LIMIT  (0)
-#endif
-
-
-#ifdef BLDCFG_PLAT_NUM_IO_APICS
-  #define CFG_PLAT_NUM_IO_APICS            BLDCFG_PLAT_NUM_IO_APICS
-#else
-  #define CFG_PLAT_NUM_IO_APICS            3
-#endif
-
-#ifdef BLDCFG_MEM_INIT_PSTATE
-  #define CFG_MEM_INIT_PSTATE              BLDCFG_MEM_INIT_PSTATE
-#else
-  #define CFG_MEM_INIT_PSTATE              0
-#endif
-
-#ifdef BLDCFG_PLATFORM_C1E_MODE
-  #define CFG_C1E_MODE                        BLDCFG_PLATFORM_C1E_MODE
-#else
-  #define CFG_C1E_MODE                        C1eModeDisabled
-#endif
-
-#ifdef BLDCFG_PLATFORM_C1E_OPDATA
-  #define CFG_C1E_OPDATA                      BLDCFG_PLATFORM_C1E_OPDATA
-#else
-  #define CFG_C1E_OPDATA                      0
-#endif
-
-#ifdef BLDCFG_PLATFORM_C1E_OPDATA1
-  #define CFG_C1E_OPDATA1                     BLDCFG_PLATFORM_C1E_OPDATA1
-#else
-  #define CFG_C1E_OPDATA1                     0
-#endif
-
-#ifdef BLDCFG_PLATFORM_C1E_OPDATA2
-  #define CFG_C1E_OPDATA2                     BLDCFG_PLATFORM_C1E_OPDATA2
-#else
-  #define CFG_C1E_OPDATA2                     0
-#endif
-
-#ifdef BLDCFG_PLATFORM_CSTATE_MODE
-  #define CFG_CSTATE_MODE                     BLDCFG_PLATFORM_CSTATE_MODE
-#else
-  #define CFG_CSTATE_MODE                     CStateModeC6
-#endif
-
-#ifdef BLDCFG_PLATFORM_CSTATE_OPDATA
-  #define CFG_CSTATE_OPDATA                   BLDCFG_PLATFORM_CSTATE_OPDATA
-#else
-  #define CFG_CSTATE_OPDATA                   0x840
-#endif
-
-#ifdef BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS
-  #define CFG_CSTATE_IO_BASE_ADDRESS       BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS
-#else
-  #define CFG_CSTATE_IO_BASE_ADDRESS       0x840
-#endif
-
-#ifdef BLDCFG_PLATFORM_CPB_MODE
-  #define CFG_CPB_MODE                        BLDCFG_PLATFORM_CPB_MODE
-#else
-  #define CFG_CPB_MODE                        CpbModeAuto
-#endif
-
-#ifdef BLDCFG_CORE_LEVELING_MODE
-  #define CFG_CORE_LEVELING_MODE           BLDCFG_CORE_LEVELING_MODE
-#else
-  #define CFG_CORE_LEVELING_MODE           CORE_LEVEL_LOWEST
-#endif
-
-#ifdef BLDCFG_AMD_PSTATE_CAP_VALUE
-  #define CFG_AMD_PSTATE_CAP_VALUE           BLDCFG_AMD_PSTATE_CAP_VALUE
-#else
-  #define CFG_AMD_PSTATE_CAP_VALUE           0
-#endif
-
-#ifdef BLDCFG_HEAP_DRAM_ADDRESS
-  #define CFG_HEAP_DRAM_ADDRESS                 BLDCFG_HEAP_DRAM_ADDRESS
-#else
-  #define CFG_HEAP_DRAM_ADDRESS                 AMD_HEAP_RAM_ADDRESS
-#endif
-
-#ifdef BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT
-  #define CFG_MEMORY_BUS_FREQUENCY_LIMIT        BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT
-#else
-  #define CFG_MEMORY_BUS_FREQUENCY_LIMIT        DDR1333_FREQUENCY
-#endif
-
-#ifdef BLDCFG_MEMORY_MODE_UNGANGED
-  #define CFG_MEMORY_MODE_UNGANGED              BLDCFG_MEMORY_MODE_UNGANGED
-#else
-  #define CFG_MEMORY_MODE_UNGANGED              TRUE
-#endif
-
-#ifdef BLDCFG_MEMORY_QUAD_RANK_CAPABLE
-  #define CFG_MEMORY_QUAD_RANK_CAPABLE          BLDCFG_MEMORY_QUAD_RANK_CAPABLE
-#else
-  #define CFG_MEMORY_QUAD_RANK_CAPABLE          TRUE
-#endif
-
-#ifdef BLDCFG_MEMORY_QUADRANK_TYPE
-  #define CFG_MEMORY_QUADRANK_TYPE              BLDCFG_MEMORY_QUADRANK_TYPE
-#else
-  #define CFG_MEMORY_QUADRANK_TYPE              QUADRANK_UNBUFFERED
-#endif
-
-#ifdef BLDCFG_MEMORY_RDIMM_CAPABLE
-  #define CFG_MEMORY_RDIMM_CAPABLE              BLDCFG_MEMORY_RDIMM_CAPABLE
-#else
-  #define CFG_MEMORY_RDIMM_CAPABLE              TRUE
-#endif
-
-#ifdef BLDCFG_MEMORY_LRDIMM_CAPABLE
-  #define CFG_MEMORY_LRDIMM_CAPABLE              BLDCFG_MEMORY_LRDIMM_CAPABLE
-#else
-  #define CFG_MEMORY_LRDIMM_CAPABLE              TRUE
-#endif
-
-#ifdef BLDCFG_MEMORY_UDIMM_CAPABLE
-  #define CFG_MEMORY_UDIMM_CAPABLE              BLDCFG_MEMORY_UDIMM_CAPABLE
-#else
-  #define CFG_MEMORY_UDIMM_CAPABLE              TRUE
-#endif
-
-#ifdef BLDCFG_MEMORY_SODIMM_CAPABLE
-  #define CFG_MEMORY_SODIMM_CAPABLE             BLDCFG_MEMORY_SODIMM_CAPABLE
-#else
-  #define CFG_MEMORY_SODIMM_CAPABLE             FALSE
-#endif
-
-#ifdef BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING
-  #define CFG_MEMORY_ENABLE_BANK_INTERLEAVING   BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING
-#else
-  #define CFG_MEMORY_ENABLE_BANK_INTERLEAVING   TRUE
-#endif
-
-#ifdef BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING
-  #define CFG_MEMORY_ENABLE_NODE_INTERLEAVING   BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING
-#else
-  #define CFG_MEMORY_ENABLE_NODE_INTERLEAVING   FALSE
-#endif
-
-#ifdef BLDCFG_MEMORY_CHANNEL_INTERLEAVING
-  #define CFG_MEMORY_CHANNEL_INTERLEAVING       BLDCFG_MEMORY_CHANNEL_INTERLEAVING
-#else
-  #define CFG_MEMORY_CHANNEL_INTERLEAVING       TRUE
-#endif
-
-#ifdef BLDCFG_MEMORY_POWER_DOWN
-  #define CFG_MEMORY_POWER_DOWN                 BLDCFG_MEMORY_POWER_DOWN
-#else
-  #define CFG_MEMORY_POWER_DOWN                 TRUE
-#endif
-
-#ifdef BLDCFG_POWER_DOWN_MODE
-  #define CFG_POWER_DOWN_MODE                   BLDCFG_POWER_DOWN_MODE
-#else
-  #define CFG_POWER_DOWN_MODE                   POWER_DOWN_BY_CHIP_SELECT
-#endif
-
-#ifdef BLDCFG_ONLINE_SPARE
-  #define CFG_ONLINE_SPARE                      BLDCFG_ONLINE_SPARE
-#else
-  #define CFG_ONLINE_SPARE                      FALSE
-#endif
-
-#ifdef BLDCFG_MEMORY_PARITY_ENABLE
-  #define CFG_MEMORY_PARITY_ENABLE              BLDCFG_MEMORY_PARITY_ENABLE
-#else
-  #define CFG_MEMORY_PARITY_ENABLE              FALSE
-#endif
-
-#ifdef BLDCFG_BANK_SWIZZLE
-  #define CFG_BANK_SWIZZLE                      BLDCFG_BANK_SWIZZLE
-#else
-  #define CFG_BANK_SWIZZLE                      TRUE
-#endif
-
-#ifdef BLDCFG_TIMING_MODE_SELECT
-  #define CFG_TIMING_MODE_SELECT                BLDCFG_TIMING_MODE_SELECT
-#else
-  #define CFG_TIMING_MODE_SELECT                TIMING_MODE_AUTO
-#endif
-
-#ifdef BLDCFG_MEMORY_CLOCK_SELECT
-  #define CFG_MEMORY_CLOCK_SELECT               BLDCFG_MEMORY_CLOCK_SELECT
-#else
-  #define CFG_MEMORY_CLOCK_SELECT               DDR1333_FREQUENCY
-#endif
-
-#ifdef BLDCFG_DQS_TRAINING_CONTROL
-  #define CFG_DQS_TRAINING_CONTROL              BLDCFG_DQS_TRAINING_CONTROL
-#else
-  #define CFG_DQS_TRAINING_CONTROL              TRUE
-#endif
-
-#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_CUSTOM)
-  #undef BLDCFG_IGNORE_SPD_CHECKSUM
-  #define BLDCFG_IGNORE_SPD_CHECKSUM            TRUE
-#endif
-
-#ifdef BLDCFG_IGNORE_SPD_CHECKSUM
-  #define CFG_IGNORE_SPD_CHECKSUM               BLDCFG_IGNORE_SPD_CHECKSUM
-#else
-  #define CFG_IGNORE_SPD_CHECKSUM               FALSE
-#endif
-
-#ifdef BLDCFG_USE_BURST_MODE
-  #define CFG_USE_BURST_MODE                    BLDCFG_USE_BURST_MODE
-#else
-  #define CFG_USE_BURST_MODE                    FALSE
-#endif
-
-#ifdef BLDCFG_MEMORY_ALL_CLOCKS_ON
-  #define CFG_MEMORY_ALL_CLOCKS_ON              BLDCFG_MEMORY_ALL_CLOCKS_ON
-#else
-  #define CFG_MEMORY_ALL_CLOCKS_ON              FALSE
-#endif
-
-#ifdef BLDCFG_ENABLE_ECC_FEATURE
-  #define CFG_ENABLE_ECC_FEATURE                BLDCFG_ENABLE_ECC_FEATURE
-#else
-  #define CFG_ENABLE_ECC_FEATURE                TRUE
-#endif
-
-#ifdef BLDCFG_ECC_REDIRECTION
-  #define CFG_ECC_REDIRECTION                   BLDCFG_ECC_REDIRECTION
-#else
-  #define CFG_ECC_REDIRECTION                   FALSE
-#endif
-
-#ifdef BLDCFG_SCRUB_DRAM_RATE
-  #define CFG_SCRUB_DRAM_RATE         BLDCFG_SCRUB_DRAM_RATE
-#else
-  #define CFG_SCRUB_DRAM_RATE         (0)
-#endif
-
-#ifdef BLDCFG_SCRUB_L2_RATE
-  #define CFG_SCRUB_L2_RATE           BLDCFG_SCRUB_L2_RATE
-#else
-  #define CFG_SCRUB_L2_RATE           (0)
-#endif
-
-#ifdef BLDCFG_SCRUB_L3_RATE
-  #define CFG_SCRUB_L3_RATE           BLDCFG_SCRUB_L3_RATE
-#else
-  #define CFG_SCRUB_L3_RATE           (0)
-#endif
-
-#ifdef BLDCFG_SCRUB_IC_RATE
-  #define CFG_SCRUB_IC_RATE           BLDCFG_SCRUB_IC_RATE
-#else
-  #define CFG_SCRUB_IC_RATE           (0)
-#endif
-
-#ifdef BLDCFG_SCRUB_DC_RATE
-  #define CFG_SCRUB_DC_RATE           BLDCFG_SCRUB_DC_RATE
-#else
-  #define CFG_SCRUB_DC_RATE           (0)
-#endif
-
-#ifdef BLDCFG_ECC_SYNC_FLOOD
-  #define CFG_ECC_SYNC_FLOOD          BLDCFG_ECC_SYNC_FLOOD
-#else
-  #define CFG_ECC_SYNC_FLOOD          FALSE
-#endif
-
-#ifdef BLDCFG_ECC_SYMBOL_SIZE
-  #define CFG_ECC_SYMBOL_SIZE         BLDCFG_ECC_SYMBOL_SIZE
-#else
-  #define CFG_ECC_SYMBOL_SIZE         0
-#endif
-
-#ifdef BLDCFG_1GB_ALIGN
-  #define CFG_1GB_ALIGN               BLDCFG_1GB_ALIGN
-#else
-  #define CFG_1GB_ALIGN               FALSE
-#endif
-
-#ifdef BLDCFG_UMA_ALLOCATION_MODE
-  #define CFG_UMA_MODE                BLDCFG_UMA_ALLOCATION_MODE
-#else
-  #define CFG_UMA_MODE                UMA_AUTO
-#endif
-
-#ifdef BLDCFG_UMA_ALLOCATION_SIZE
-  #define CFG_UMA_SIZE                BLDCFG_UMA_ALLOCATION_SIZE
-#else
-  #define CFG_UMA_SIZE                0
-#endif
-
-#ifdef BLDCFG_UMA_ABOVE4G_SUPPORT
-  #define CFG_UMA_ABOVE4G           BLDCFG_UMA_ABOVE4G_SUPPORT
-#else
-  #define CFG_UMA_ABOVE4G           FALSE
-#endif
-
-#ifdef BLDCFG_UMA_ALIGNMENT
-  #define CFG_UMA_ALIGNMENT           BLDCFG_UMA_ALIGNMENT
-#else
-  #define CFG_UMA_ALIGNMENT           NO_UMA_ALIGNED
-#endif
-
-#ifdef BLDCFG_PROCESSOR_SCOPE_IN_SB
-  #define CFG_PROCESSOR_SCOPE_IN_SB   BLDCFG_PROCESSOR_SCOPE_IN_SB
-#else
-  #define CFG_PROCESSOR_SCOPE_IN_SB   FALSE
-#endif
-
-#ifdef BLDCFG_S3_LATE_RESTORE
-  #define CFG_S3_LATE_RESTORE         BLDCFG_S3_LATE_RESTORE
-#else
-  #define CFG_S3_LATE_RESTORE         TRUE
-#endif
-
-#ifdef BLDCFG_USE_32_BYTE_REFRESH
-  #define CFG_USE_32_BYTE_REFRESH  (BLDCFG_USE_32_BYTE_REFRESH)
-#else
-  #define CFG_USE_32_BYTE_REFRESH  (FALSE)
-#endif
-
-#ifdef BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY
-  #define CFG_USE_VARIABLE_MCT_ISOC_PRIORITY  (BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY)
-#else
-  #define CFG_USE_VARIABLE_MCT_ISOC_PRIORITY  (FALSE)
-#endif
-
-#ifdef BLDCFG_PROCESSOR_SCOPE_NAME0
-  #define CFG_PROCESSOR_SCOPE_NAME0          BLDCFG_PROCESSOR_SCOPE_NAME0
-#else
-  #define CFG_PROCESSOR_SCOPE_NAME0          SCOPE_NAME_VALUE
-#endif
-
-#ifdef BLDCFG_PROCESSOR_SCOPE_NAME1
-  #define CFG_PROCESSOR_SCOPE_NAME1          BLDCFG_PROCESSOR_SCOPE_NAME1
-#else
-  #define CFG_PROCESSOR_SCOPE_NAME1          SCOPE_NAME_VALUE1
-#endif
-
-#ifdef BLDCFG_CFG_GNB_HD_AUDIO
-  #define CFG_GNB_HD_AUDIO                   BLDCFG_CFG_GNB_HD_AUDIO
-#else
-  #define CFG_GNB_HD_AUDIO                   TRUE
-#endif
-
-#ifdef BLDCFG_CFG_ABM_SUPPORT
-  #define CFG_ABM_SUPPORT                    BLDCFG_CFG_ABM_SUPPORT
-#else
-  #define CFG_ABM_SUPPORT                    FALSE
-#endif
-
-#ifdef BLDCFG_CFG_DYNAMIC_REFRESH_RATE
-  #define CFG_DINAMIC_REFRESH_RATE           BLDCFG_CFG_DYNAMIC_REFRESH_RATE
-#else
-  #define CFG_DYNAMIC_REFRESH_RATE           0
-#endif
-
-#ifdef BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL
-  #define CFG_LCD_BACK_LIGHT_CONTROL         BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL
-#else
-  #define CFG_LCD_BACK_LIGHT_CONTROL         0
-#endif
-
-#ifdef BLDCFG_STEREO_3D_PINOUT
-  #define CFG_GNB_STEREO_3D_PINOUT           BLDCFG_STEREO_3D_PINOUT
-#else
-  #define CFG_GNB_STEREO_3D_PINOUT           0
-#endif
-
-#ifdef BLDCFG_IGPU_SUBSYSTEM_ID
-  #define CFG_GNB_IGPU_SSID                  BLDCFG_IGPU_SUBSYSTEM_ID
-#else
-  #define CFG_GNB_IGPU_SSID                  0
-#endif
-
-#ifdef BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID
-  #define CFG_GNB_HDAUDIO_SSID               BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID
-#else
-  #define CFG_GNB_HDAUDIO_SSID               0
-#endif
-
-#ifdef BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID
-  #define CFG_GNB_PCIE_SSID                  BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID
-#else
-  #define CFG_GNB_PCIE_SSID                  0x12341022
-#endif
-
-#ifdef BLDCFG_GFX_LVDS_SPREAD_SPECTRUM
-  #define CFG_GFX_LVDS_SPREAD_SPECTRUM               BLDCFG_GFX_LVDS_SPREAD_SPECTRUM
-#else
-  #define CFG_GFX_LVDS_SPREAD_SPECTRUM               0
-#endif
-
-#ifdef BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE
-  #define CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE               BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE
-#else
-  #define CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE               0
-#endif
-
-#ifdef BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM
-  #define CFG_PCIE_REFCLK_SPREAD_SPECTRUM               BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM
-#else
-  #define CFG_PCIE_REFCLK_SPREAD_SPECTRUM               0
-#endif
-
-#ifdef BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS
-  #define CFG_TEMP_PCIE_MMIO_BASE_ADDRESS    BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS
-#else
-  #define CFG_TEMP_PCIE_MMIO_BASE_ADDRESS    0xD0000000
-#endif
-
-#ifdef BLDOPT_REMOVE_EARLY_SAMPLES
-  #if  BLDOPT_REMOVE_EARLY_SAMPLES == TRUE
-    #undef  OPTION_EARLY_SAMPLES
-    #define OPTION_EARLY_SAMPLES        FALSE
-  #else
-    #undef  OPTION_EARLY_SAMPLES
-    #define OPTION_EARLY_SAMPLES        TRUE
-  #endif
-#endif
-
-#ifdef BLDOPT_REMOVE_ALIB
-  #if  BLDOPT_REMOVE_ALIB == TRUE
-    #undef  OPTION_ALIB
-    #define OPTION_ALIB                 FALSE
-  #else
-    #undef  OPTION_ALIB
-    #define OPTION_ALIB                 TRUE
-  #endif
-#endif
-
-#ifdef BLDCFG_LVDS_MISC_888_FPDI_MODE
-  #define CFG_LVDS_MISC_888_FPDI_MODE                 BLDCFG_LVDS_MISC_888_FPDI_MODE
-#else
-  #define CFG_LVDS_MISC_888_FPDI_MODE                 FALSE
-#endif
-
-#ifdef BLDCFG_LVDS_MISC_DL_CH_SWAP
-  #define CFG_LVDS_MISC_DL_CH_SWAP                 BLDCFG_LVDS_MISC_DL_CH_SWAP
-#else
-  #define CFG_LVDS_MISC_DL_CH_SWAP                 FALSE
-#endif
-
-#ifdef BLDCFG_LVDS_MISC_VSYNC_ACTIVE_LOW
-  #define CFG_LVDS_MISC_VSYNC_ACTIVE_LOW                 BLDCFG_LVDS_MISC_VSYNC_ACTIVE_LOW
-#else
-  #define CFG_LVDS_MISC_VSYNC_ACTIVE_LOW                 FALSE
-#endif
-
-#ifdef BLDCFG_LVDS_MISC_HSYNC_ACTIVE_LOW
-  #define CFG_LVDS_MISC_HSYNC_ACTIVE_LOW                 BLDCFG_LVDS_MISC_HSYNC_ACTIVE_LOW
-#else
-  #define CFG_LVDS_MISC_HSYNC_ACTIVE_LOW                 FALSE
-#endif
-
-#ifdef BLDCFG_LVDS_MISC_BLON_ACTIVE_LOW
-  #define CFG_LVDS_MISC_BLON_ACTIVE_LOW                 BLDCFG_LVDS_MISC_BLON_ACTIVE_LOW
-#else
-  #define CFG_LVDS_MISC_BLON_ACTIVE_LOW                 FALSE
-#endif
-
-#ifdef BLDCFG_PLATFORM_POWER_POLICY_MODE
-  #define CFG_PLATFORM_POWER_POLICY_MODE  (BLDCFG_PLATFORM_POWER_POLICY_MODE)
-#else
-  #define CFG_PLATFORM_POWER_POLICY_MODE  (Performance)
-#endif
-
-#define CFG_PCI_MMIO_BASE                 (CONFIG_ECAM_MMCONF_BASE_ADDRESS)
-
-#define CFG_PCI_MMIO_SIZE                 (CONFIG_ECAM_MMCONF_BUS_NUMBER)
-
-#ifdef BLDCFG_AP_MTRR_SETTINGS_LIST
-  #define CFG_AP_MTRR_SETTINGS_LIST           (BLDCFG_AP_MTRR_SETTINGS_LIST)
-#else
-  #define CFG_AP_MTRR_SETTINGS_LIST           (&OntarioApMtrrSettingsList)
-#endif
-
-/*---------------------------------------------------------------------------
- *       Processing the options:  Third, perform the option cross checks
- *--------------------------------------------------------------------------*/
-// Check that deprecated options are not used
-#ifdef BLDCFG_PCI_MMIO_BASE
-  #error  BLDOPT: BLDCFG_PCI_MMIO_BASE has been deprecated in coreboot. Do not use!
-#endif
-#ifdef BLDCFG_PCI_MMIO_SIZE
-  #error  BLDOPT: BLDCFG_PCI_MMIO_SIZE has been deprecated in coreboot. Do not use!
-#endif
-// Assure that at least one type of memory support is included
-#if OPTION_UDIMMS == FALSE
-  #if OPTION_RDIMMS == FALSE
-    #if OPTION_SODIMMS == FALSE
-      #if OPTION_LRDIMMS == FALSE
-        #error  BLDOPT: No DIMM support selected. Either BLDOPT_REMOVE_UDIMMS_SUPPORT or BLDOPT_REMOVE_RDIMMS_SUPPORT or BLDOPT_REMOVE_SODIMMS_SUPPORT or BLDOPT_REMOVE_LRDIMMS_SUPPORT must be FALSE.
-      #endif
-    #endif
-  #endif
-#endif
-// Ensure at least one dimm type is capable
-#if CFG_MEMORY_RDIMM_CAPABLE == FALSE
-  #if CFG_MEMORY_UDIMM_CAPABLE == FALSE
-    #if CFG_MEMORY_SODIMM_CAPABLE == FALSE
-      #if CFG_MEMORY_LRDIMM_CAPABLE == FALSE
-        #error   BLDCFG: No dimm type is capable
-      #endif
-    #endif
-  #endif
-#endif
-//  Turn off multi-socket based features if only one node...
-#if OPTION_MULTISOCKET == FALSE
-  #undef  OPTION_PARALLEL_TRAINING
-  #define OPTION_PARALLEL_TRAINING    FALSE
-  #undef  OPTION_NODE_INTERLEAVE
-  #define OPTION_NODE_INTERLEAVE      FALSE
-#endif
-// Ensure that at least one write leveling option is selected
-#if OPTION_DDR3 == TRUE
-  #if OPTION_HW_WRITE_LEV_TRAINING == FALSE
-    #if OPTION_SW_WRITE_LEV_TRAINING == FALSE
-      #error  No Write leveling option selected for DDR3
-    #endif
-  #endif
-  #if OPTION_SW_DRAM_INIT == FALSE
-    #error   Software dram init must be enabled for DDR3 dimms
-  #endif
-#endif
-// Ensure at least one DQS receiver training option is selected
-#if OPTION_HW_DQS_REC_EN_TRAINING == FALSE
-  #if OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == FALSE
-    #if OPTION_OPT_SW_DQS_REC_EN_TRAINING == FALSE
-      #error    No DQS receiver training option has been slected
-    #endif
-  #endif
-#endif
-// Ensure at least one Rd Wr position training option has been selected
-#if OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == FALSE
-  #if OPTION_OPT_SW_RD_WR_POS_TRAINING == FALSE
-    #error    No Rd Wr position training option has been selected
-  #endif
-#endif
-// Ensure at least one dram init option has been selected
-#if OPTION_HW_DRAM_INIT == FALSE
-  #if OPTION_SW_DRAM_INIT == FALSE
-    #error    No Dram init option has been selected
-  #endif
-#endif
-// Ensure the frequency limit is valid
-#if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1866_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 933)
-  #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1600_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 800)
-    #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1333_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 667)
-      #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1066_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 533)
-        #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR800_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 400)
-          #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR667_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 333)
-            #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR533_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 266)
-              #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR400_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 200)
-                #error    BLDCFG: Unsupported memory bus frequency
-              #endif
-            #endif
-          #endif
-        #endif
-      #endif
-    #endif
-  #endif
-#endif
-// Ensure timing mode is valid
-#if CFG_TIMING_MODE_SELECT != TIMING_MODE_SPECIFIC
-  #if CFG_TIMING_MODE_SELECT != TIMING_MODE_LIMITED
-    #if CFG_TIMING_MODE_SELECT != TIMING_MODE_AUTO
-      #error    BLDCFG: Invalid timing mode is set
-    #endif
-  #endif
-#endif
-// Ensure the scrub rate is valid
-#if ((CFG_SCRUB_DRAM_RATE > 0x16) && (CFG_SCRUB_DRAM_RATE != 0xFF))
-  #error    BLDCFG: Unsupported dram scrub rate set
-#endif
-#if CFG_SCRUB_L2_RATE > 0x16
-  #error   BLDCFG: Unsupported L2 scrubber rate set
-#endif
-#if CFG_SCRUB_L3_RATE > 0x16
-  #error   BLDCFG: unsupported L3 scrubber rate set
-#endif
-#if CFG_SCRUB_IC_RATE > 0x16
-  #error    BLDCFG: Unsupported Instruction cache scrub rate set
-#endif
-#if CFG_SCRUB_DC_RATE > 0x16
-  #error   BLDCFG: Unsupported Dcache scrub rate set
-#endif
-// Ensure Quad rank dimm type is valid
-#if CFG_MEMORY_QUADRANK_TYPE != QUADRANK_UNBUFFERED
-  #if CFG_MEMORY_QUADRANK_TYPE != QUADRANK_REGISTERED
-    #error     BLDCFG: Invalid quad rank dimm type set
-  #endif
-#endif
-// Ensure ECC symbol size is valid
-#if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_USE_BKDG
-  #if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_FORCE_X4
-    #if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_FORCE_X8
-      #error   BLDCFG: Invalid Ecc symbol size set
-    #endif
-  #endif
-#endif
-// Ensure power down mode is valid
-#if CFG_POWER_DOWN_MODE != POWER_DOWN_BY_CHIP_SELECT
-  #if CFG_POWER_DOWN_MODE != POWER_DOWN_BY_CHANNEL
-    #error     BLDCFG: Invalid power down mode set
-  #endif
-#endif
-
-/*****************************************************************************
- *
- * Process the option logic, setting local control variables
- *
- ****************************************************************************/
-#if OPTION_ACPI_PSTATES == TRUE
-  #define OPTFCN_ACPI_TABLES           CreateAcpiTablesMain
-  #define OPTFCN_GATHER_DATA           PStateGatherData
-  #if OPTION_MULTISOCKET == TRUE
-    #define OPTFCN_PSTATE_LEVELING     PStateLeveling
-  #else
-    #define OPTFCN_PSTATE_LEVELING     CommonReturnAgesaSuccess
-  #endif
-#else
-  #define OPTFCN_ACPI_TABLES           CommonReturnAgesaSuccess
-  #define OPTFCN_GATHER_DATA           CommonReturnAgesaSuccess
-  #define OPTFCN_PSTATE_LEVELING       CommonReturnAgesaSuccess
-#endif
-
-
-/*****************************************************************************
- *
- * Include the structure definitions for the defaults table structures
- *
- ****************************************************************************/
-#include <CommonReturns.h>
-#include <agesa-entry-cfg.h>
-#include  "Options.h"
-#include  "OptionCpuFamiliesInstall.h"
-#include  "OptionsHt.h"
-#include  "OptionHtInstall.h"
-#include  "OptionMemory.h"
-#include  "OptionMemoryInstall.h"
-#include  "OptionCpuFeaturesInstall.h"
-#include  "OptionDmi.h"
-#include  "OptionDmiInstall.h"
-#include  "OptionPstate.h"
-#include  "OptionPstateInstall.h"
-#include  "OptionWhea.h"
-#include  "OptionWheaInstall.h"
-#include  "OptionSrat.h"
-#include  "OptionSratInstall.h"
-#include  "OptionSlit.h"
-#include  "OptionSlitInstall.h"
-#include  "OptionMultiSocket.h"
-#include  "OptionMultiSocketInstall.h"
-#include  "OptionIdsInstall.h"
-#include  "OptionGfxRecovery.h"
-#include  "OptionGfxRecoveryInstall.h"
-#include  "OptionGnb.h"
-#include  "OptionGnbInstall.h"
-#include  "OptionS3ScriptInstall.h"
-
-
-/*****************************************************************************
- *
- *  Generate the output structures (defaults tables)
- *
- ****************************************************************************/
-CONST BUILD_OPT_CFG UserOptions = {
-  {                                             // AGESA version string
-    AGESA_CODE_SIGNATURE,                       //    code header Signature
-    AGESA_PACKAGE_STRING,                       //    8 character ID
-    AGESA_VERSION_STRING,                       //    12 character version string
-    0                                           //    null string terminator
-  },
-  //Build Option Area
-  OPTION_UDIMMS,                        //UDIMMS
-  OPTION_RDIMMS,                        //RDIMMS
-  OPTION_LRDIMMS,                       //LRDIMMS
-  OPTION_ECC,                           //ECC
-  OPTION_BANK_INTERLEAVE,               //BANK_INTERLEAVE
-  OPTION_DCT_INTERLEAVE,                //DCT_INTERLEAVE
-  OPTION_NODE_INTERLEAVE,               //NODE_INTERLEAVE
-  OPTION_PARALLEL_TRAINING,             //PARALLEL_TRAINING
-  OPTION_ONLINE_SPARE,                  //ONLINE_SPARE
-  OPTION_MEM_RESTORE,                   //MEM CONTEXT RESTORE
-  OPTION_MULTISOCKET,                   //MULTISOCKET
-  OPTION_ACPI_PSTATES,                  //ACPI_PSTATES
-  OPTION_SRAT,                          //SRAT
-  OPTION_SLIT,                          //SLIT
-  OPTION_WHEA,                          //WHEA
-  OPTION_DMI,                           //DMI
-  OPTION_EARLY_SAMPLES,                 //EARLY_SAMPLES
-  OPTION_ADDR_TO_CS_TRANSLATOR,         //ADDR_TO_CS_TRANSLATOR
-
-  //Build Configuration Area
-  CFG_PCI_MMIO_BASE,
-  CFG_PCI_MMIO_SIZE,
-  {
-    // CoreVrm
-    {
-      CFG_VRM_CURRENT_LIMIT,              // VrmCurrentLimit
-      CFG_VRM_LOW_POWER_THRESHOLD,        // VrmLowPowerThershold
-      CFG_VRM_SLEW_RATE,                  // VrmSlewRate
-      CFG_VRM_ADDITIONAL_DELAY,           // VrmAdditionalDelay
-      CFG_VRM_HIGH_SPEED_ENABLE,          // VrmHiSpeedEnable
-      CFG_VRM_INRUSH_CURRENT_LIMIT        // VrmInrushCurrentLimit
-    },
-    // NbVrm
-    {
-      CFG_VRM_NB_CURRENT_LIMIT,           // VrmNbCurrentLimit
-      CFG_VRM_NB_LOW_POWER_THRESHOLD,     // VrmNbLowPowerThershold
-      CFG_VRM_NB_SLEW_RATE,               // VrmNbSlewRate
-      CFG_VRM_NB_ADDITIONAL_DELAY,        // VrmNbAdditionalDelay
-      CFG_VRM_NB_HIGH_SPEED_ENABLE,       // VrmNbHiSpeedEnable
-      CFG_VRM_NB_INRUSH_CURRENT_LIMIT     // VrmNbInrushCurrentLimit
-    }
-  },
-  CFG_PLAT_NUM_IO_APICS,                //PlatformApicIoNumber
-  CFG_MEM_INIT_PSTATE,                  //MemoryInitPstate
-  CFG_C1E_MODE,                         //C1eMode
-  CFG_C1E_OPDATA,                       //C1ePlatformData
-  CFG_C1E_OPDATA1,                      //C1ePlatformData1
-  CFG_C1E_OPDATA2,                      //C1ePlatformData2
-  CFG_CSTATE_MODE,                      //CStateMode
-  CFG_CSTATE_OPDATA,                    //CStatePlatformData
-  CFG_CSTATE_IO_BASE_ADDRESS,           //CStateIoBaseAddress
-  CFG_CPB_MODE,                         //CpbMode
-  CFG_CORE_LEVELING_MODE,               //CoreLevelingCofig
-  {
-    CFG_PLATFORM_CONTROL_FLOW_MODE,       // The platform's control flow mode.
-    CFG_USE_HT_ASSIST,                    // CfgUseHtAssist
-    CFG_USE_ATM_MODE,                     // CfgUseAtmMode
-    CFG_USE_32_BYTE_REFRESH,              // Display Refresh uses 32 byte packets.
-    CFG_USE_VARIABLE_MCT_ISOC_PRIORITY,   // The Memory controller will be set to Variable Isoc Priority.
-    CFG_PLATFORM_POWER_POLICY_MODE        // The platform's power policy mode.
-  },
-  (CPU_HT_DEEMPHASIS_LEVEL *)CFG_PLATFORM_DEEMPHASIS_LIST,         // Deemphasis settings
-  CFG_AMD_PLATFORM_TYPE,                //AmdPlatformType
-  CFG_AMD_PSTATE_CAP_VALUE,             // Amd pstate ceiling enabling deck
-
-  CFG_MEMORY_BUS_FREQUENCY_LIMIT,       // CfgMemoryBusFrequencyLimit
-  CFG_MEMORY_MODE_UNGANGED,             // CfgMemoryModeUnganged
-  CFG_MEMORY_QUAD_RANK_CAPABLE,         // CfgMemoryQuadRankCapable
-  CFG_MEMORY_QUADRANK_TYPE,             // CfgMemoryQuadrankType
-  CFG_MEMORY_RDIMM_CAPABLE,             // CfgMemoryRDimmCapable
-  CFG_MEMORY_LRDIMM_CAPABLE,            // CfgMemoryLRDimmCapable
-  CFG_MEMORY_UDIMM_CAPABLE,             // CfgMemoryUDimmCapable
-  CFG_MEMORY_SODIMM_CAPABLE,            // CfgMemorySodimmCapable
-  CFG_MEMORY_ENABLE_BANK_INTERLEAVING,  // CfgMemoryEnableBankInterleaving
-  CFG_MEMORY_ENABLE_NODE_INTERLEAVING,  // CfgMemoryEnableNodeInterleaving
-  CFG_MEMORY_CHANNEL_INTERLEAVING,      // CfgMemoryChannelInterleaving
-  CFG_MEMORY_POWER_DOWN,                // CfgMemoryPowerDown
-  CFG_POWER_DOWN_MODE,                  // CfgPowerDownMode
-  CFG_ONLINE_SPARE,                     // CfgOnlineSpare
-  CFG_MEMORY_PARITY_ENABLE,             // CfgMemoryParityEnable
-  CFG_BANK_SWIZZLE,                     // CfgBankSwizzle
-  CFG_TIMING_MODE_SELECT,               // CfgTimingModeSelect
-  CFG_MEMORY_CLOCK_SELECT,              // CfgMemoryClockSelect
-  CFG_DQS_TRAINING_CONTROL,             // CfgDqsTrainingControl
-  CFG_IGNORE_SPD_CHECKSUM,              // CfgIgnoreSpdChecksum
-  CFG_USE_BURST_MODE,                   // CfgUseBurstMode
-  CFG_MEMORY_ALL_CLOCKS_ON,             // CfgMemoryAllClocksOn
-  CFG_ENABLE_ECC_FEATURE,               // CfgEnableEccFeature
-  CFG_ECC_REDIRECTION,                  // CfgEccRedirection
-  CFG_SCRUB_DRAM_RATE,                  // CfgScrubDramRate
-  CFG_SCRUB_L2_RATE,                    // CfgScrubL2Rate
-  CFG_SCRUB_L3_RATE,                    // CfgScrubL3Rate
-  CFG_SCRUB_IC_RATE,                    // CfgScrubIcRate
-  CFG_SCRUB_DC_RATE,                    // CfgScrubDcRate
-  CFG_ECC_SYNC_FLOOD,                   // CfgEccSyncFlood
-  CFG_ECC_SYMBOL_SIZE,                  // CfgEccSymbolSize
-  CFG_HEAP_DRAM_ADDRESS,                // CfgHeapDramAddress
-  CFG_1GB_ALIGN,                        // CfgNodeMem1GBAlign
-  CFG_S3_LATE_RESTORE,                  // CfgS3LateRestore
-  CFG_ACPI_PSTATE_PSD_INDPX,            // CfgAcpiPstateIndependent
-  (AP_MTRR_SETTINGS *) CFG_AP_MTRR_SETTINGS_LIST, // CfgApMtrrSettingsList
-  CFG_UMA_MODE,                         // CfgUmaMode
-  CFG_UMA_SIZE,                         // CfgUmaSize
-  CFG_UMA_ABOVE4G,                      // CfgUmaAbove4G
-  CFG_UMA_ALIGNMENT,                    // CfgUmaAlignment
-  CFG_PROCESSOR_SCOPE_IN_SB,            // CfgProcessorScopeInSb
-  CFG_PROCESSOR_SCOPE_NAME0,            // CfgProcessorScopeName0
-  CFG_PROCESSOR_SCOPE_NAME1,            // CfgProcessorScopeName1
-  CFG_GNB_HD_AUDIO,                     // CfgGnbHdAudio
-  CFG_ABM_SUPPORT,                      // CfgAbmSupport
-  CFG_DYNAMIC_REFRESH_RATE,             // CfgDynamicRefreshRate
-  CFG_LCD_BACK_LIGHT_CONTROL,           // CfgLcdBackLightControl
-  CFG_GNB_STEREO_3D_PINOUT,             // CfgGnb3dStereoPinIndex
-  CFG_TEMP_PCIE_MMIO_BASE_ADDRESS,      // CfgTempPcieMmioBaseAddress
-  CFG_GNB_IGPU_SSID,                    // CfgGnbIGPUSSID
-  CFG_GNB_HDAUDIO_SSID,                 // CfgGnbHDAudioSSID
-  CFG_GNB_PCIE_SSID,                    // CfgGnbPcieSSID
-  CFG_GFX_LVDS_SPREAD_SPECTRUM,         // CfgLvdsSpreadSpectrum
-  CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE,    // CfgLvdsSpreadSpectrumRate
-
-  {{
-	CFG_LVDS_MISC_888_FPDI_MODE,          // CfgLvdsMiscControl
-	CFG_LVDS_MISC_DL_CH_SWAP,             // CfgLvdsMiscControl
-	CFG_LVDS_MISC_VSYNC_ACTIVE_LOW,       // CfgLvdsMiscControl
-	CFG_LVDS_MISC_HSYNC_ACTIVE_LOW,       // CfgLvdsMiscControl
-	CFG_LVDS_MISC_BLON_ACTIVE_LOW,        // CfgLvdsMiscControl
-  }},
-  CFG_PCIE_REFCLK_SPREAD_SPECTRUM,      // CfgPcieRefClkSpreadSpectrum
-  0,                                    //reserved...
-};
-
-
-CONST DISPATCH_TABLE ROMDATA ApDispatchTable[] =
-{
-  IDS_LATE_RUN_AP_TASK
-  // Get DMI info
-  CPU_DMI_AP_GET_TYPE4_TYPE7
-  // Probe filter enable
-  HT_ASSIST_AP_DISABLE_CACHE
-  HT_ASSIST_AP_ENABLE_CACHE
-
-  { 0, NULL }
-};
-
-#if AGESA_ENTRY_INIT_RESET == TRUE
-  #if IDSOPT_IDS_ENABLED == TRUE
-    #if IDSOPT_TRACING_ENABLED == TRUE
-      #define MAKE_DBG_STR(x, y)  MAKE_AS_A_STRING(x : y)
-      CONST CHAR8 * CONST BldOptDebugOutput[] = {
-        #if IDS_TRACE_SHOW_BLD_OPT_CFG == TRUE
-          //Build Option Area
-          MAKE_DBG_STR (\nOptUDIMM,             OPTION_UDIMMS)
-          MAKE_DBG_STR (\nOptRDIMM,             OPTION_RDIMMS)
-          MAKE_DBG_STR (\nOptLRDIMM,            OPTION_LRDIMMS)
-          MAKE_DBG_STR (\nOptECC,               OPTION_ECC)
-          MAKE_DBG_STR (\nOptCsIntlv,           OPTION_BANK_INTERLEAVE)
-          MAKE_DBG_STR (\nOptDctIntlv,          OPTION_DCT_INTERLEAVE)
-          MAKE_DBG_STR (\nOptNodeIntlv,         OPTION_NODE_INTERLEAVE)
-          //MAKE_DBG_STR (\nOptParallelTraining,  OPTION_PARALLEL_TRAINING)
-          MAKE_DBG_STR (\nOptOnlineSpare,       OPTION_ONLINE_SPARE)
-          MAKE_DBG_STR (\nOptAddr2CsTranslator, OPTION_ADDR_TO_CS_TRANSLATOR)
-          MAKE_DBG_STR (\nOptMemRestore,        OPTION_MEM_RESTORE)
-          MAKE_DBG_STR (\nOptMultiSocket,       OPTION_MULTISOCKET)
-          MAKE_DBG_STR (\nOptPstates,           OPTION_ACPI_PSTATES)
-          MAKE_DBG_STR (\nOptSRAT,              OPTION_SRAT)
-          MAKE_DBG_STR (\nOptSLIT,              OPTION_SLIT)
-          MAKE_DBG_STR (\nOptWHEA,              OPTION_WHEA)
-          MAKE_DBG_STR (\nOptDMI,               OPTION_DMI)
-          MAKE_DBG_STR (\nOptEarlySamples,      OPTION_EARLY_SAMPLES),
-
-          //Build Configuration Area
-          // CoreVrm
-          MAKE_DBG_STR (\nVrmCurrentLimit      , CFG_VRM_CURRENT_LIMIT)
-          MAKE_DBG_STR (\nVrmLowPowerThreshold , CFG_VRM_LOW_POWER_THRESHOLD)
-          MAKE_DBG_STR (\nVrmSlewRate          , CFG_VRM_SLEW_RATE)
-          MAKE_DBG_STR (\nVrmAdditionalDelay   , CFG_VRM_ADDITIONAL_DELAY)
-          MAKE_DBG_STR (\nVrmHiSpeedEnable     , CFG_VRM_HIGH_SPEED_ENABLE)
-          MAKE_DBG_STR (\nVrmInrushCurrentLimit, CFG_VRM_INRUSH_CURRENT_LIMIT)
-          // NbVrm
-          MAKE_DBG_STR (\nNbVrmCurrentLimit      , CFG_VRM_NB_CURRENT_LIMIT)
-          MAKE_DBG_STR (\nNbVrmLowPowerThreshold , CFG_VRM_NB_LOW_POWER_THRESHOLD)
-          MAKE_DBG_STR (\nNbVrmSlewRate          , CFG_VRM_NB_SLEW_RATE)
-          MAKE_DBG_STR (\nNbVrmAdditionalDelay   , CFG_VRM_NB_ADDITIONAL_DELAY)
-          MAKE_DBG_STR (\nNbVrmHiSpeedEnable     , CFG_VRM_NB_HIGH_SPEED_ENABLE)
-          MAKE_DBG_STR (\nNbVrmInrushCurrentLimit, CFG_VRM_NB_INRUSH_CURRENT_LIMIT),
-
-          MAKE_DBG_STR (\nNumIoApics            , CFG_PLAT_NUM_IO_APICS)
-          MAKE_DBG_STR (\nMemInitPstate         , CFG_MEM_INIT_PSTATE)
-          MAKE_DBG_STR (\nC1eMode               , CFG_C1E_MODE)
-          MAKE_DBG_STR (\nC1eOpData             , CFG_C1E_OPDATA)
-          MAKE_DBG_STR (\nC1eOpdata1            , CFG_C1E_OPDATA1)
-          MAKE_DBG_STR (\nC1eOpdata2            , CFG_C1E_OPDATA2)
-          MAKE_DBG_STR (\nCStateMode            , CFG_CSTATE_MODE)
-          MAKE_DBG_STR (\nCStateOpData          , CFG_CSTATE_OPDATA)
-          MAKE_DBG_STR (\nCStateIoBaseAddr      , CFG_CSTATE_IO_BASE_ADDRESS)
-          MAKE_DBG_STR (\nCpbMode               , CFG_CPB_MODE)
-          MAKE_DBG_STR (\nCoreLevelingMode      , CFG_CORE_LEVELING_MODE),
-
-          MAKE_DBG_STR (\nControlFlowMode       , CFG_PLATFORM_CONTROL_FLOW_MODE)
-          MAKE_DBG_STR (\nUseHtAssist           , CFG_USE_HT_ASSIST)
-          MAKE_DBG_STR (\nUseAtmMode            , CFG_USE_ATM_MODE)
-          MAKE_DBG_STR (\nUse32ByteRefresh      , CFG_USE_32_BYTE_REFRESH)
-          MAKE_DBG_STR (\nUseVarMctIsocPriority , CFG_USE_VARIABLE_MCT_ISOC_PRIORITY)
-          MAKE_DBG_STR (\nPowerPolicy           , CFG_PLATFORM_POWER_POLICY_MOD)
-
-          MAKE_DBG_STR (\nDeemphasisList        , CFG_PLATFORM_DEEMPHASIS_LIST)
-
-          MAKE_DBG_STR (\nPciMmioAddr           , CFG_PCI_MMIO_BASE)
-          MAKE_DBG_STR (\nPciMmioSize           , CFG_PCI_MMIO_SIZE)
-          MAKE_DBG_STR (\nPlatformType          , CFG_AMD_PLATFORM_TYPE)
-          MAKE_DBG_STR (\nPstateCapValue        , CFG_AMD_PSTATE_CAP_VALUE),
-
-          MAKE_DBG_STR (\nMemBusFreqLimit       , CFG_MEMORY_BUS_FREQUENCY_LIMIT)
-          MAKE_DBG_STR (\nTimingModeSelect      , CFG_TIMING_MODE_SELECT)
-          MAKE_DBG_STR (\nMemoryClockSelect     , CFG_MEMORY_CLOCK_SELECT)
-
-          MAKE_DBG_STR (\nMemUnganged           , CFG_MEMORY_MODE_UNGANGED)
-          MAKE_DBG_STR (\nQRCap                 , CFG_MEMORY_QUAD_RANK_CAPABLE)
-          MAKE_DBG_STR (\nQRType                , CFG_MEMORY_QUADRANK_TYPE)
-          MAKE_DBG_STR (\nRDimmCap              , CFG_MEMORY_RDIMM_CAPABLE)
-          MAKE_DBG_STR (\nLRDimmCap             , CFG_MEMORY_LRDIMM_CAPABLE)
-          MAKE_DBG_STR (\nUDimmCap              , CFG_MEMORY_UDIMM_CAPABLE)
-          MAKE_DBG_STR (\nSODimmCap             , CFG_MEMORY_SODIMM_CAPABLE)
-          MAKE_DBG_STR (\nDqsTrainingControl    , CFG_DQS_TRAINING_CONTROL)
-          MAKE_DBG_STR (\nIgnoreSpdChecksum     , CFG_IGNORE_SPD_CHECKSUM)
-          MAKE_DBG_STR (\nUseBurstMode          , CFG_USE_BURST_MODE)
-          MAKE_DBG_STR (\nAllMemClkOn           , CFG_MEMORY_ALL_CLOCKS_ON),
-
-          MAKE_DBG_STR (\nPowerDownEn           , CFG_MEMORY_POWER_DOWN)
-          MAKE_DBG_STR (\nPowerDownMode         , CFG_POWER_DOWN_MODE)
-          MAKE_DBG_STR (\nOnlineSpare           , CFG_ONLINE_SPARE)
-          MAKE_DBG_STR (\nAddrParityEn          , CFG_MEMORY_PARITY_ENABLE)
-          MAKE_DBG_STR (\nBankSwizzle           , CFG_BANK_SWIZZLE)
-          MAKE_DBG_STR (\nCsIntlvEn             , CFG_MEMORY_ENABLE_BANK_INTERLEAVING)
-          MAKE_DBG_STR (\nNodeIntlvEn           , CFG_MEMORY_ENABLE_NODE_INTERLEAVING)
-          MAKE_DBG_STR (\nDctIntlvEn            , CFG_MEMORY_CHANNEL_INTERLEAVING),
-
-          MAKE_DBG_STR (\nUmaMode                , CFG_UMA_MODE)
-          MAKE_DBG_STR (\nUmaSize                , CFG_UMA_SIZE)
-          MAKE_DBG_STR (\nUmaAbove4G             , CFG_UMA_ABOVE4G)
-          MAKE_DBG_STR (\nUmaAlignment           , CFG_UMA_ALIGNMENT)
-
-          MAKE_DBG_STR (\nEccEn                 , CFG_ENABLE_ECC_FEATURE)
-          MAKE_DBG_STR (\nEccRedirect           , CFG_ECC_REDIRECTION)
-          MAKE_DBG_STR (\nScrubDramRate         , CFG_SCRUB_DRAM_RATE)
-          MAKE_DBG_STR (\nScrubL2Rate           , CFG_SCRUB_L2_RATE)
-          MAKE_DBG_STR (\nScrubL3Rate           , CFG_SCRUB_L3_RATE)
-          MAKE_DBG_STR (\nScrubIcRate           , CFG_SCRUB_IC_RATE)
-          MAKE_DBG_STR (\nScrubDcRate           , CFG_SCRUB_DC_RATE)
-          MAKE_DBG_STR (\nEccSyncFlood          , CFG_ECC_SYNC_FLOOD)
-          MAKE_DBG_STR (\nEccSymbolSize         , CFG_ECC_SYMBOL_SIZE)
-          MAKE_DBG_STR (\nHeapDramAddress       , CFG_HEAP_DRAM_ADDRESS)
-          MAKE_DBG_STR (\nNodeMem1GBAlign       , CFG_1GB_ALIGN),
-
-          MAKE_DBG_STR (\nS3LateRestore         , CFG_S3_LATE_RESTORE)
-          MAKE_DBG_STR (\nAcpiPstateIndependent , CFG_ACPI_PSTATE_PSD_INDPX)
-
-          MAKE_DBG_STR (\nApMtrrSettingsList     , CFG_AP_MTRR_SETTINGS_LIST)
-
-          MAKE_DBG_STR (\nProcessorScopeInSb     , CFG_PROCESSOR_SCOPE_IN_SB)
-          MAKE_DBG_STR (\nProcessorScopeName0    , CFG_PROCESSOR_SCOPE_NAME0)
-          MAKE_DBG_STR (\nProcessorScopeName1    , CFG_PROCESSOR_SCOPE_NAME1)
-          MAKE_DBG_STR (\nGnbHdAudio             , CFG_GNB_HD_AUDIO)
-          MAKE_DBG_STR (\nAbmSupport             , CFG_ABM_SUPPORT)
-          MAKE_DBG_STR (\nDynamicRefreshRate     , CFG_DYNAMIC_REFRESH_RATE)
-          MAKE_DBG_STR (\nLcdBackLightControl    , CFG_LCD_BACK_LIGHT_CONTROL)
-          MAKE_DBG_STR (\nGnb3dStereoPinIndex    , CFG_GNB_STEREO_3D_PINOUT)
-          MAKE_DBG_STR (\nTempPcieMmioBaseAddress, CFG_TEMP_PCIE_MMIO_BASE_ADDRESS),
-          MAKE_DBG_STR (\nCfgGnbIGPUSSID         , CFG_GNB_IGPU_SSID),
-          MAKE_DBG_STR (\nCfgGnbHDAudioSSID      , CFG_GNB_HDAUDIO_SSID),
-          MAKE_DBG_STR (\nCfgGnbPcieSSID         , CFG_GNB_PCIE_SSID),
-
-          MAKE_DBG_STR (\nCfgLvdsSpreadSpectrum  , CFG_GFX_LVDS_SPREAD_SPECTRUM),
-          MAKE_DBG_STR (\nCfgLvdsSpreadSpectrumRate , CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE),
-          MAKE_DBG_STR (\nCfgLvdsMiscControl.FpdiMode   , CFG_LVDS_MISC_888_FPDI_MODE),
-          MAKE_DBG_STR (\nCfgLvdsMiscControl.DlChSwap           , CFG_LVDS_MISC_DL_CH_SWAP),
-          MAKE_DBG_STR (\nCfgLvdsMiscControl.VsyncActiveLow     , CFG_LVDS_MISC_VSYNC_ACTIVE_LOW),
-          MAKE_DBG_STR (\nCfgLvdsMiscControl.HsyncActiveLow     , CFG_LVDS_MISC_HSYNC_ACTIVE_LOW),
-          MAKE_DBG_STR (\nCfgLvdsMiscControl.BLONActiveLow      , CFG_LVDS_MISC_BLON_ACTIVE_LOW),
-          MAKE_DBG_STR (\nCfgPcieRefClkSpreadSpectrum   , CFG_PCIE_REFCLK_SPREAD_SPECTRUM),
-        #endif
-        NULL
-      };
-    #endif
-  #endif
-#endif