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authorPaul Menzel <paulepanter@users.sourceforge.net>2013-04-12 14:03:04 +0200
committerRonald G. Minnich <rminnich@gmail.com>2013-04-14 19:28:50 +0200
commit0b3128679688b76f8fc92a770615270707a80afd (patch)
tree86bbe90da8d6792d8c4dcaa777e177bb1e82f11c /src/vendorcode/amd/cimx/sb800
parentcb891de07ffe605897010776fc1becc9589d3648 (diff)
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AMD CIMx sb800/SATA.c, sb900/Sata.c: Fix R*AI*D typo in comments
Spell RAID correctly in comments. Found with the following command. $ git grep -i riad Change-Id: I68e8476d885a88df589d25f88cc158d71eb04e07 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3081 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/vendorcode/amd/cimx/sb800')
-rw-r--r--src/vendorcode/amd/cimx/sb800/SATA.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/vendorcode/amd/cimx/sb800/SATA.c b/src/vendorcode/amd/cimx/sb800/SATA.c
index b7bbacdbdb84..4aa3be7fccb1 100644
--- a/src/vendorcode/amd/cimx/sb800/SATA.c
+++ b/src/vendorcode/amd/cimx/sb800/SATA.c
@@ -469,7 +469,7 @@ sataInitAfterPciEnum (
RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG34), AccWidthUint8 | S3_SAVE, 0, 0x70);
if (((pConfig->SataClass) != NATIVE_IDE_MODE) && ((pConfig->SataClass) != LEGACY_IDE_MODE)) {
- // RIAD or AHCI
+ // RAID or AHCI
if ((pConfig->SATAMODE.SataMode.SataIdeCombinedMode) == SATA_IDE_COMBINE_DISABLE) {
RWMEM ((ddBar5 + SB_SATA_BAR5_REG00), AccWidthUint8 | S3_SAVE, ~(BIT2 + BIT1 + BIT0), BIT2 + BIT0);
RWMEM ((ddBar5 + SB_SATA_BAR5_REG0C), AccWidthUint8 | S3_SAVE, 0xC0, 0x3F);