diff options
| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2016-10-15 09:20:43 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-11-07 20:36:13 +0100 |
| commit | a04006513008ef72a863bc0eb04e6d4f729ca8ab (patch) | |
| tree | 7b1ac3072d8c478954b5f7550ff09c6469e7727f /src/vendorcode/amd/pi/00670F00/Include | |
| parent | 9ef6e52353dbbcfac727e0207dbbcc07dfb75d47 (diff) | |
| download | coreboot-a04006513008ef72a863bc0eb04e6d4f729ca8ab.tar.gz coreboot-a04006513008ef72a863bc0eb04e6d4f729ca8ab.tar.bz2 coreboot-a04006513008ef72a863bc0eb04e6d4f729ca8ab.zip | |
vendorcode/amd: Copy 00670F00 files from PI package
Make exact copies of the AGESA files from the Stoney PI package
replacing existing versions. Change the license text and fix
up misc. whitespace.
This will facilitate the review of binaryPI changes in the
vendorcode directory.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from commit 1097249585ab76fab59dcfbf8e7a419f34fcfcb6)
Change-Id: I9951df58aeab2d533efc0a837ce35f343ff28d7c
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/17194
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/vendorcode/amd/pi/00670F00/Include')
7 files changed, 201 insertions, 37 deletions
diff --git a/src/vendorcode/amd/pi/00670F00/Include/Filecode.h b/src/vendorcode/amd/pi/00670F00/Include/Filecode.h index 0e01812626c0..74e60f7d0bdf 100644 --- a/src/vendorcode/amd/pi/00670F00/Include/Filecode.h +++ b/src/vendorcode/amd/pi/00670F00/Include/Filecode.h @@ -12,11 +12,11 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: Include - * @e \$Revision: 309899 $ @e \$Date: 2014-12-23 02:21:13 -0600 (Tue, 23 Dec 2014) $ + * @e \$Revision$ @e \$Date$ */ /***************************************************************************** * - * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc. + * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -129,7 +129,8 @@ #define PROC_GNB_MODULES_GNBPCIETRAININGV2_PCIETRAININGV2_FILECODE (0xA101) #define PROC_GNB_MODULES_GNBPCIETRAININGV2_PCIEWORKAROUNDSV2_FILECODE (0xA102) -#define PROC_GNB_MODULES_GNBINITCZ_ALIBCZ_FILECODE (0xA202) +#define PROC_GNB_MODULES_GNBINITCZ_ALIBCZD_FILECODE (0xA201) +#define PROC_GNB_MODULES_GNBINITCZ_ALIBCZM_FILECODE (0xA202) #define PROC_GNB_MODULES_GNBINITCZ_GFXENVINITCZ_FILECODE (0xA203) #define PROC_GNB_MODULES_GNBINITCZ_GFXGMCINITCZ_FILECODE (0xA204) #define PROC_GNB_MODULES_GNBINITCZ_GFXINTEGRATEDINFOTABLECZ_FILECODE (0xA205) @@ -159,6 +160,35 @@ #define PROC_GNB_MODULES_GNBINITCZ_GNBPSPCZ_FILECODE (0xA21E) #define PROC_GNB_MODULES_GNBINITCZ_GNBSMUINITCZ_FILECODE (0xA21F) +#define PROC_GNB_MODULES_GNBINITST_ALIBST_FILECODE (0xA300) +#define PROC_GNB_MODULES_GNBINITST_GFXENVINITST_FILECODE (0xA301) +#define PROC_GNB_MODULES_GNBINITST_GFXGMCINITST_FILECODE (0xA302) +#define PROC_GNB_MODULES_GNBINITST_GFXINTEGRATEDINFOTABLEST_FILECODE (0xA303) +#define PROC_GNB_MODULES_GNBINITST_GFXLIBST_FILECODE (0xA304) +#define PROC_GNB_MODULES_GNBINITST_GFXMIDINITST_FILECODE (0xA305) +#define PROC_GNB_MODULES_GNBINITST_GFXPOSTINITST_FILECODE (0xA306) +#define PROC_GNB_MODULES_GNBINITST_GNBEARLYINITST_FILECODE (0xA307) +#define PROC_GNB_MODULES_GNBINITST_GNBENVINITST_FILECODE (0xA308) +#define PROC_GNB_MODULES_GNBINITST_GNBFUSETABLEST_FILECODE (0xA309) +#define PROC_GNB_MODULES_GNBINITST_GNBIOMMUIVRSST_FILECODE (0xA30A) +#define PROC_GNB_MODULES_GNBINITST_GNBMIDINITST_FILECODE (0xA30B) +#define PROC_GNB_MODULES_GNBINITST_GNBPOSTINITST_FILECODE (0xA30C) +#define PROC_GNB_MODULES_GNBINITST_GNBREGISTERACCST_FILECODE (0xA30D) +#define PROC_GNB_MODULES_GNBINITST_GNBURATOKENMAPST_FILECODE (0xA30E) +#define PROC_GNB_MODULES_GNBINITST_PCIECOMPLEXDATAST_FILECODE (0xA30F) +#define PROC_GNB_MODULES_GNBINITST_PCIECONFIGST_FILECODE (0xA310) +#define PROC_GNB_MODULES_GNBINITST_PCIEEARLYINITST_FILECODE (0xA311) +#define PROC_GNB_MODULES_GNBINITST_PCIEENVINITST_FILECODE (0xA312) +#define PROC_GNB_MODULES_GNBINITST_PCIELIBST_FILECODE (0xA313) +#define PROC_GNB_MODULES_GNBINITST_PCIEMIDINITST_FILECODE (0xA314) +#define PROC_GNB_MODULES_GNBINITST_PCIEPOSTINITST_FILECODE (0xA315) +#define PROC_GNB_MODULES_GNBINITST_PCIEPOWERGATEST_FILECODE (0xA316) +#define PROC_GNB_MODULES_GNBINITST_GNBURAST_FILECODE (0xA317) +#define PROC_GNB_MODULES_GNBINITST_PCIEARIINITST_FILECODE (0xA318) +#define PROC_GNB_MODULES_GNBINITST_GNBBOOTTIMECALST_FILECODE (0xA319) +#define PROC_GNB_MODULES_GNBINITST_GNBPSPST_FILECODE (0xA31A) +#define PROC_GNB_MODULES_GNBINITST_GNBSMUINITST_FILECODE (0xA31B) + #define PROC_RECOVERY_GNB_GNBRECOVERY_FILECODE (0xAE01) #define PROC_RECOVERY_GNB_NBINITRECOVERY_FILECODE (0xAE02) #define PROC_GNB_GNBINITATRTB_FILECODE (0xAE03) @@ -447,6 +477,31 @@ #define PROC_CPU_FAMILY_0X15_CZ_CPUF15CZCONNECTEDSTANDBY_FILECODE (0xCB89) #define PROC_CPU_FAMILY_0X15_CZ_CPUF15CZBTC_FILECODE (0xCB8A) +#define PROC_CPU_FAMILY_0X15_ST_CPUF15STCOREAFTERRESET_FILECODE (0xCB90) +#define PROC_CPU_FAMILY_0X15_ST_CPUF15STDMI_FILECODE (0xCB91) +#define PROC_CPU_FAMILY_0X15_ST_CPUF15STNBAFTERRESET_FILECODE (0xCB92) +#define PROC_CPU_FAMILY_0X15_ST_CPUF15STPSTATE_FILECODE (0xCB93) +#define PROC_CPU_FAMILY_0X15_ST_CPUF15STLOGICALIDTABLES_FILECODE (0xCB94) +#define PROC_CPU_FAMILY_0X15_ST_CPUF15STMICROCODEPATCHTABLES_FILECODE (0xCB95) +#define PROC_CPU_FAMILY_0X15_ST_CPUF15STALLCORETABLES_FILECODE (0xCB96) +#define PROC_CPU_FAMILY_0X15_ST_CPUF15STCOMPUTEUNITTABLES_FILECODE (0xCB97) +#define PROC_CPU_FAMILY_0X15_ST_CPUF15STEQUIVALENCETABLE_FILECODE (0xCB98) +#define PROC_CPU_FAMILY_0X15_ST_CPUF15STPRIMARYCORETABLES_FILECODE (0xCB99) +#define PROC_CPU_FAMILY_0X15_ST_CPUF15STPOWERMGMTSYSTEMTABLES_FILECODE (0xCB9A) +#define PROC_CPU_FAMILY_0X15_ST_CPUF15STUTILITIES_FILECODE (0xCB9C) +#define PROC_CPU_FAMILY_0X15_ST_CPUF15STC6STATE_FILECODE (0xCB9D) +#define PROC_CPU_FAMILY_0X15_ST_CPUF15STCPB_FILECODE (0xCB9E) +#define PROC_CPU_FAMILY_0X15_ST_CPUF15STIOCSTATE_FILECODE (0xCB9F) +#define PROC_CPU_FAMILY_0X15_ST_CPUF15STCACHEFLUSHONHALT_FILECODE (0xCBA0) +#define PROC_CPU_FAMILY_0X15_ST_CPUF15STHTC_FILECODE (0xCBA1) +#define PROC_CPU_FAMILY_0X15_ST_CPUF15STINITEARLYTABLE_FILECODE (0xCBA2) +#define PROC_CPU_FAMILY_0X15_ST_CPUF15STEARLYSAMPLES_FILECODE (0xCBA3) +#define PROC_CPU_FAMILY_0X15_ST_CPUF15STPSI_FILECODE (0xCBA5) +#define PROC_CPU_FAMILY_0X15_ST_CPUF15STWORKAROUNDTABLE_FILECODE (0xCBA7) +#define PROC_CPU_FAMILY_0X15_ST_CPUF15STCC6EXITCONTROL_FILECODE (0xCBA8) +#define PROC_CPU_FAMILY_0X15_ST_CPUF15STCONNECTEDSTANDBY_FILECODE (0xCBA9) +#define PROC_CPU_FAMILY_0X15_ST_CPUF15STBTC_FILECODE (0xCBAA) + #define PROC_CPU_FEATURE_CPUCACHEFLUSHONHALT_FILECODE (0xDC01) #define PROC_CPU_FEATURE_CPUCACHEINIT_FILECODE (0xDC02) #define PROC_CPU_FEATURE_CPUDMI_FILECODE (0xDC10) @@ -491,6 +546,7 @@ #define PROC_IDS_DEBUG_IDSIDTTABLE_FILECODE (0xE81E) #define PROC_IDS_CONTROL_IDSNVTOCMOS_FILECODE (0xE81F) #define PROC_IDS_FAMILY_0X15_CZ_IDSF15CZALLSERVICE_FILECODE (0xE821) +#define PROC_IDS_FAMILY_0X15_ST_IDSF15STALLSERVICE_FILECODE (0xE822) ///0xE820 ~ 0xE840 is reserved for ids extend module @@ -523,13 +579,16 @@ #define PROC_MEM_FEAT_RDWR2DTRAINING_MFRDWR2DPATTERNGENERATION_FILECODE (0xF09C) #define PROC_MEM_FEAT_AGGRESSOR_MFAGGRESSOR_FILECODE (0xF09F) #define PROC_MEM_FEAT_DLLPDBYPASS_MFDLLPDBYPASS_FILECODE (0xF0A0) +#define PROC_MEM_FEAT_LVDDR4_MFLVDDR4_FILECODE (0xF0A1) #define PROC_MEM_MAIN_MDEF_FILECODE (0xF101) #define PROC_MEM_MAIN_MINIT_FILECODE (0xF102) #define PROC_MEM_MAIN_MM_FILECODE (0xF103) #define PROC_MEM_FEAT_DMI_MFDMI_FILECODE (0xF104) -#define PROC_MEM_MAIN_MMECC_FILECODE (0xF105) -#define PROC_MEM_MAIN_MMEXCLUDEDIMM_FILECODE (0xF106) +#define PROC_MEM_FEAT_DMI_MFDMID4_FILECODE (0xF105) +#define PROC_MEM_FEAT_DMI_MFDMID34_FILECODE (0xF106) +#define PROC_MEM_MAIN_MMECC_FILECODE (0xF107) +#define PROC_MEM_MAIN_MMEXCLUDEDIMM_FILECODE (0xF108) #define PROC_MEM_MAIN_MMNODEINTERLEAVE_FILECODE (0xF10B) #define PROC_MEM_MAIN_MMONLINESPARE_FILECODE (0xF10C) #define PROC_MEM_MAIN_MMPARALLELTRAINING_FILECODE (0xF10D) @@ -543,7 +602,13 @@ #define PROC_MEM_MAIN_MMMEMRESTORE_FILECODE (0xF117) #define PROC_MEM_MAIN_MMCONDITIONALPSO_FILECODE (0xF118) #define PROC_MEM_MAIN_MMAGGRESSOR_FILECODE (0xF119) +#define PROC_MEM_MAIN_MMLVDDR4_FILECODE (0xF11A) #define PROC_MEM_MAIN_CZ_MMFLOWD3CZ_FILECODE (0xF127) +#define PROC_MEM_MAIN_ST_MMFLOWD3ST_FILECODE (0xF129) +#define PROC_MEM_MAIN_CZ_MMFLOWD4CZ_FILECODE (0xF12A) +#define PROC_MEM_MAIN_CZ_MMFLOWD34CZ_FILECODE (0xF12B) +#define PROC_MEM_MAIN_ST_MMFLOWD4ST_FILECODE (0xF12C) +#define PROC_MEM_MAIN_ST_MMFLOWD34ST_FILECODE (0xF12D) #define PROC_MEM_NB_MN_FILECODE (0XF27C) #define PROC_MEM_NB_MNDCT_FILECODE (0XF27D) @@ -554,19 +619,48 @@ #define PROC_MEM_NB_MNFEAT_FILECODE (0XF282) #define PROC_MEM_NB_MNTRAIN3_FILECODE (0XF284) #define PROC_MEM_NB_MNREG_FILECODE (0XF285) -#define PROC_MEM_NB_MNPMU_FILECODE (0xF2B7) -#define PROC_MEM_NB_CZ_MNCZ_FILECODE (0xF2D8) -#define PROC_MEM_NB_CZ_MNDCTCZ_FILECODE (0xF2D9) -#define PROC_MEM_NB_CZ_MNIDENDIMMCZ_FILECODE (0xF2DA) -#define PROC_MEM_NB_CZ_MNMCTCZ_FILECODE (0xF2DB) -#define PROC_MEM_NB_CZ_MNPHYCZ_FILECODE (0xF2DC) -#define PROC_MEM_NB_CZ_MNPMUCZ_FILECODE (0xF2DD) -#define PROC_MEM_NB_CZ_MNPMUSRAMMSGBLOCKCZ_FILECODE (0xF2DE) -#define PROC_MEM_NB_CZ_MNPROTOCZ_FILECODE (0xF2DF) -#define PROC_MEM_NB_CZ_MNREGCZ_FILECODE (0xF2E0) -#define PROC_MEM_NB_CZ_MNS3CZ_FILECODE (0xF2E1) -#define PROC_MEM_NB_CZ_MNPSPCZ_FILECODE (0XF2E3) - +#define PROC_MEM_NB_MNPMU_FILECODE (0xF286) +#define PROC_MEM_NB_MNMRSD3_FILECODE (0xF287) +#define PROC_MEM_NB_MNMRSD4_FILECODE (0xF288) +#define PROC_MEM_NB_CZ_MNCZ_FILECODE (0xF289) +#define PROC_MEM_NB_CZ_MND3CZ_FILECODE (0xF28A) +#define PROC_MEM_NB_CZ_MND4CZ_FILECODE (0xF28B) +#define PROC_MEM_NB_CZ_MNDCTCZ_FILECODE (0xF28C) +#define PROC_MEM_NB_CZ_MNDCTD3CZ_FILECODE (0xF28D) +#define PROC_MEM_NB_CZ_MNDCTD4CZ_FILECODE (0xF28E) +#define PROC_MEM_NB_CZ_MNIDENDIMMCZ_FILECODE (0xF28F) +#define PROC_MEM_NB_CZ_MNMCTCZ_FILECODE (0xF290) +#define PROC_MEM_NB_CZ_MNPHYCZ_FILECODE (0xF291) +#define PROC_MEM_NB_CZ_MNPHYD3CZ_FILECODE (0xF292) +#define PROC_MEM_NB_CZ_MNPHYD4CZ_FILECODE (0xF293) +#define PROC_MEM_NB_CZ_MNPMUCZ_FILECODE (0xF294) +#define PROC_MEM_NB_CZ_MNPMUD3CZ_FILECODE (0xF295) +#define PROC_MEM_NB_CZ_MNPMUD4CZ_FILECODE (0xF296) +#define PROC_MEM_NB_CZ_MNPMUSRAMMSGBLOCKCZ_FILECODE (0xF297) +#define PROC_MEM_NB_CZ_MNPROTOCZ_FILECODE (0xF298) +#define PROC_MEM_NB_CZ_MNREGCZ_FILECODE (0xF299) +#define PROC_MEM_NB_CZ_MNS3CZ_FILECODE (0xF29A) +#define PROC_MEM_NB_CZ_MNPSPCZ_FILECODE (0XF29B) + +#define PROC_MEM_NB_ST_MNST_FILECODE (0xF2E4) +#define PROC_MEM_NB_ST_MNDCTST_FILECODE (0xF2E5) +#define PROC_MEM_NB_ST_MNIDENDIMMST_FILECODE (0xF2E6) +#define PROC_MEM_NB_ST_MNMCTST_FILECODE (0xF2E7) +#define PROC_MEM_NB_ST_MNPHYST_FILECODE (0xF2E8) +#define PROC_MEM_NB_ST_MNPMUST_FILECODE (0xF2E9) +#define PROC_MEM_NB_ST_MNPMUSRAMMSGBLOCKST_FILECODE (0xF2EA) +#define PROC_MEM_NB_ST_MNPROTOST_FILECODE (0xF2EB) +#define PROC_MEM_NB_ST_MNREGST_FILECODE (0xF2EC) +#define PROC_MEM_NB_ST_MNS3ST_FILECODE (0xF2ED) +#define PROC_MEM_NB_ST_MNPSPST_FILECODE (0XF2EE) +#define PROC_MEM_NB_ST_MNDCTD3ST_FILECODE (0xF2EF) +#define PROC_MEM_NB_ST_MNDCTD4ST_FILECODE (0xF2F0) +#define PROC_MEM_NB_ST_MND3ST_FILECODE (0xF2F1) +#define PROC_MEM_NB_ST_MND4ST_FILECODE (0xF2F2) +#define PROC_MEM_NB_ST_MNPHYD3ST_FILECODE (0xF2F3) +#define PROC_MEM_NB_ST_MNPHYD4ST_FILECODE (0xF2F4) +#define PROC_MEM_NB_ST_MNPMUD3ST_FILECODE (0xF2F5) +#define PROC_MEM_NB_ST_MNPMUD4ST_FILECODE (0xF2F6) #define PROC_MEM_PS_MP_FILECODE (0XF401) #define PROC_MEM_PS_MPRTT_FILECODE (0XF422) @@ -582,13 +676,37 @@ #define PROC_MEM_PS_MPS2D_FILECODE (0XF436) #define PROC_MEM_PS_MPSEEDS_FILECODE (0XF437) #define PROC_MEM_PS_MPCADCFG_FILECODE (0XF43C) -#define PROC_MEM_PS_MPDATACFG_FILECODE (0XF43D) +#define PROC_MEM_PS_MPDATACFGD3_FILECODE (0XF43D) +#define PROC_MEM_PS_MPDATACFGD4_FILECODE (0XF43E) #define PROC_MEM_PS_CZ_MPCZ3_FILECODE (0XF445) #define PROC_MEM_PS_CZ_MPSCZ3_FILECODE (0XF446) #define PROC_MEM_PS_CZ_MPUCZ3_FILECODE (0XF447) -#define PROC_MEM_PS_CZ_FP4_MPSCZFP4_FILECODE (0XF44A) -#define PROC_MEM_PS_CZ_FP4_MPUCZFP4_FILECODE (0XF44B) +#define PROC_MEM_PS_CZ_FP4_MPSCZFP4D3_FILECODE (0XF44A) +#define PROC_MEM_PS_CZ_FP4_MPUCZFP4D3_FILECODE (0XF44B) +#define PROC_MEM_PS_CZ_MPCZ4_FILECODE (0XF44C) +#define PROC_MEM_PS_CZ_MPSCZ4_FILECODE (0XF44D) +#define PROC_MEM_PS_CZ_FP4_MPSCZFP4D4_FILECODE (0XF44F) +#define PROC_MEM_PS_CZ_FP4_MPUCZFP4D4_FILECODE (0XF450) + +#define PROC_MEM_PS_ST_MPST3_FILECODE (0XF451) +#define PROC_MEM_PS_ST_MPSST3_FILECODE (0XF452) +#define PROC_MEM_PS_ST_MPUST3_FILECODE (0XF453) +#define PROC_MEM_PS_ST_FP4_MPSSTFP4D3_FILECODE (0XF454) +#define PROC_MEM_PS_ST_FP4_MPUSTFP4D3_FILECODE (0XF455) +#define PROC_MEM_PS_ST_FP4_MPSSTFP4D4_FILECODE (0XF456) +#define PROC_MEM_PS_ST_FP4_MPUSTFP4D4_FILECODE (0XF457) + +#define PROC_MEM_PS_CZ_AM4_MPUCZAM4D3_FILECODE (0XF458) +#define PROC_MEM_PS_CZ_AM4_MPUCZAM4D4_FILECODE (0XF459) + +#define PROC_MEM_PS_ST_FT4_MPSSTFT4D3_FILECODE (0XF45A) +#define PROC_MEM_PS_ST_FT4_MPSSTFT4D4_FILECODE (0XF45B) + +#define PROC_MEM_PS_ST_FT4_MPUSTFT4D3_FILECODE (0XF45C) +#define PROC_MEM_PS_ST_FT4_MPUSTFT4D4_FILECODE (0XF45D) +#define PROC_MEM_PS_CZ_MPUCZ4_FILECODE (0XF45E) +#define PROC_MEM_PS_ST_MPSST4_FILECODE (0XF45F) #define PROC_MEM_TECH_MT_FILECODE (0XF501) #define PROC_MEM_TECH_MTHDI_FILECODE (0XF502) @@ -611,6 +729,8 @@ #define PROC_MEM_TECH_MTTRDDQS2DTRAINING_FILECODE (0XF58B) #define PROC_MEM_TECH_MTTRDDQS2DEYERIMSEARCH_FILECODE (0XF58C) +#define PROC_MEM_TECH_DDR4_MT4_FILECODE (0XF58D) +#define PROC_MEM_TECH_DDR4_MTSPD4_FILECODE (0XF58E) #define PROC_MEM_X86_MEMINITLIBX86_FILECODE (0xF590) #define PROC_MEM_A57_MEMINITLIBA57_FILECODE (0xF591) diff --git a/src/vendorcode/amd/pi/00670F00/Include/GeneralServices.h b/src/vendorcode/amd/pi/00670F00/Include/GeneralServices.h index aea946a784aa..683ed64618e3 100644 --- a/src/vendorcode/amd/pi/00670F00/Include/GeneralServices.h +++ b/src/vendorcode/amd/pi/00670F00/Include/GeneralServices.h @@ -10,12 +10,12 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: Common - * @e \$Revision: 309090 $ @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $ + * @e \$Revision$ @e \$Date$ * */ /***************************************************************************** * - * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc. + * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/src/vendorcode/amd/pi/00670F00/Include/Ids.h b/src/vendorcode/amd/pi/00670F00/Include/Ids.h index cb101869e351..69c06ec9c338 100644 --- a/src/vendorcode/amd/pi/00670F00/Include/Ids.h +++ b/src/vendorcode/amd/pi/00670F00/Include/Ids.h @@ -9,11 +9,11 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: IDS - * @e \$Revision: 309899 $ @e \$Date: 2014-12-23 02:21:13 -0600 (Tue, 23 Dec 2014) $ + * @e \$Revision$ @e \$Date$ */ /***************************************************************************** * - * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc. + * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -223,7 +223,13 @@ typedef enum { //vv- for debug reference only IDS_AFTER_DQS_TRAINING, ///< a7 override any settings after DQS training IDS_OVERRIDE_DIMM_MASK, ///< a8 override DimmMask for S3 data blob creation IDS_BYPASS_S3_REGISTERS, ///< a9 bypass restoring certain registers - IDS_OPTION_END ///< AA End of IDS option + IDS_MEM_RTTNOM, ///< aa Hook for Override RttNom + IDS_MEM_RTTWR, ///< ab Hook for Override RttWr + IDS_MEM_RTTPARK, ///< ac Hook for Override RttPark + IDS_MEM_ADDR_CMD_TMG, ///< ad Address command timing + IDS_MEM_MR6_VREF_DQ, ///< ae MR6 VRefDQ + IDS_MEM_PMU_RETRAIN_TIMES, ///< af override memory PMU retrain times + IDS_OPTION_END ///< B0 End of IDS option } AGESA_IDS_OPTION; #include "OptionsIds.h" @@ -507,7 +513,9 @@ typedef enum { //vv- for debug reference only #define IDS_EXTENDED_HOOK(idsoption, dataptr, idsnvptr, stdheader) IDS_SUCCESS #define IDS_TRACE_DEFAULT (0) #define IDS_INITIAL_F15_CZ_PM_STEP + #define IDS_INITIAL_F15_ST_PM_STEP #define IDS_F15_CZ_PM_CUSTOM_STEP + #define IDS_F15_ST_PM_CUSTOM_STEP #define IDS_EXTENDED_GET_DATA_EARLY(data, StdHeader) #define IDS_EXTENDED_GET_DATA_LATE(data, StdHeader) #define IDS_EXTENDED_HEAP_SIZE 0 @@ -655,7 +663,7 @@ typedef enum { //vv- for debug reference only #define MEM_FLOW DEBUG_PRINT_SHIFT (2) #define MEM_STATUS DEBUG_PRINT_SHIFT (3) #define MEM_UNDEF_BF DEBUG_PRINT_SHIFT (4) -#define MEMORY_TRACE_RSV2 DEBUG_PRINT_SHIFT (5) +#define MEM_PMU DEBUG_PRINT_SHIFT (5) #define MEMORY_TRACE_RSV3 DEBUG_PRINT_SHIFT (6) #define MEMORY_TRACE_RSV4 DEBUG_PRINT_SHIFT (7) #define MEMORY_TRACE_RSV5 DEBUG_PRINT_SHIFT (8) @@ -761,10 +769,16 @@ typedef enum { //vv- for debug reference only #define MEMORY_TRACE_ALL\ (\ MEM_FLOW | MEM_GETREG | MEM_SETREG | MEM_STATUS | \ - MEMORY_TRACE_RSV1 | MEMORY_TRACE_RSV2 | MEMORY_TRACE_RSV3 | MEMORY_TRACE_RSV4 | \ + MEM_UNDEF_BF | MEM_PMU | MEMORY_TRACE_RSV3 | MEMORY_TRACE_RSV4 | \ MEMORY_TRACE_RSV5 | MEMORY_TRACE_RSV6\ ) +#define MEMORY_TRACE_DEFAULT\ + (\ + MEM_FLOW | MEM_STATUS | MEM_PMU\ + ) + + #define TOPO_TRACE_ALL\ (\ TOPO_TRACE | TOPO_TRACE_RSV1 | TOPO_TRACE_RSV2 | TOPO_TRACE_RSV3 | \ @@ -792,7 +806,7 @@ typedef enum { //vv- for debug reference only #define TRACE_MASK_ALL (0xFFFFFFFFFFFFFFFFull) #ifndef IDS_DEBUG_PRINT_MASK - #define IDS_DEBUG_PRINT_MASK (GNB_TRACE_DEFAULT | CPU_TRACE_ALL | MEM_FLOW | MEM_STATUS | TOPO_TRACE_ALL | FCH_TRACE_ALL | MAIN_FLOW | IDS_TRACE_DEFAULT | TEST_POINT | MEM_GETREG) + #define IDS_DEBUG_PRINT_MASK (GNB_TRACE_DEFAULT | CPU_TRACE_ALL | MEMORY_TRACE_DEFAULT | TOPO_TRACE_ALL | FCH_TRACE_ALL | MAIN_FLOW | IDS_TRACE_DEFAULT | TEST_POINT) #endif /// if no specific define INIT & EXIT will be NULL @@ -1121,6 +1135,7 @@ typedef enum { TpProcMemConfigureDCTNonExplicitSeq,///< 8B .. Configure DCT For Non-Explicit TpProcMemSynchronizeChannels, ///< 8C .. Configure to Sync channels TpProcMemC6StorageAllocation, ///< 8D .. Allocate C6 Storage + TpProcMemLvDdr4, ///< 8E .. Before LV DDR4 // Gnb Earlier init TpGnbEarlierPcieConfigurationInit = 0x90, ///< 90 .. GNB earlier PCIE configuration init diff --git a/src/vendorcode/amd/pi/00670F00/Include/IdsPerf.h b/src/vendorcode/amd/pi/00670F00/Include/IdsPerf.h index 0ec8a492f03b..4663f8c35c49 100644 --- a/src/vendorcode/amd/pi/00670F00/Include/IdsPerf.h +++ b/src/vendorcode/amd/pi/00670F00/Include/IdsPerf.h @@ -9,11 +9,11 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: IDS - * @e \$Revision: 309090 $ @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $ + * @e \$Revision$ @e \$Date$ */ /***************************************************************************** * - * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc. + * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/src/vendorcode/amd/pi/00670F00/Include/Options.h b/src/vendorcode/amd/pi/00670F00/Include/Options.h index 70c39f89e32e..4bd67439aac2 100644 --- a/src/vendorcode/amd/pi/00670F00/Include/Options.h +++ b/src/vendorcode/amd/pi/00670F00/Include/Options.h @@ -9,11 +9,11 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: Core - * @e \$Revision: 309090 $ @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $ + * @e \$Revision$ @e \$Date$ */ /***************************************************************************** * - * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc. + * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/src/vendorcode/amd/pi/00670F00/Include/PlatformMemoryConfiguration.h b/src/vendorcode/amd/pi/00670F00/Include/PlatformMemoryConfiguration.h index 38f7f051f48e..6a8a01789ee3 100644 --- a/src/vendorcode/amd/pi/00670F00/Include/PlatformMemoryConfiguration.h +++ b/src/vendorcode/amd/pi/00670F00/Include/PlatformMemoryConfiguration.h @@ -9,12 +9,12 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: OPTION - * @e \$Revision: 309090 $ @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $ + * @e \$Revision$ @e \$Date$ * */ /***************************************************************************** * - * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc. + * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -202,6 +202,19 @@ /// #define LAYERS_4 0x0 #define LAYERS_6 0x1 +/// DQS Routing Type +/// +#define DQS_ROUTING_TREE 0x1 ///< Tree topology is applied to DQS routing +#define DQS_ROUTING_DAISY_CHAIN 0x2 ///< Daisy chain topology is applied to DQS routing + +/// +/// DataMaskMbTypes +/// Motherboard type for processor Data Mask pins. +/// +#define DATAMASK_NO_CONNECT 0x00 ///< No connect +#define DATAMASK_DM_ROUTING 0x01 ///< Pins are routed per DM rules +#define DATAMASK_DQS_ROUTING 0x02 ///< Pins are routed per DQS rules + /*---------------------------------------------------------------------------------------- * * Platform Specific Overriding Table Definitions @@ -230,6 +243,10 @@ #define PSO_CPU_FAMILY_TO_OVERRIDE 18 ///< CPU family signature to tell following PSO macros are CPU family dependent #define PSO_MAX_SOLDERED_DOWN_DIMMS 19 ///< Max Soldered-down Dimms per channel #define PSO_MOTHER_BOARD_LAYERS 20 ///< Mother board layer design +#define PSO_ON_DIMM_THERMAL_CONTROL 21 ///< On DIMM thermal override +#define PSO_DATA_MASK_MB_TYPE 22 ///< Motherboard type for processor Data Mask pins. +#define PSO_DQS_ROUTING_TYPE 23 ///< Dqs Routing Type +#define PSO_BYPASSED_DIMM_SLOTS 24 ///< Number of bypassed Dimm slots /*---------------------------------- * CONDITIONAL PSO SPECIFIC ENTRIES @@ -303,6 +320,9 @@ #define NUMBER_OF_SOLDERED_DOWN_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfSolderedDownDimmsPerChannel) \ PSO_MAX_SOLDERED_DOWN_DIMMS, 4, SocketID, ChannelID, ALL_DIMMS, NumberOfSolderedDownDimmsPerChannel +#define NUMBER_OF_BYPASSED_DIMM_SLOTS(SocketID, ChannelID, NumberOfBypassedDimmSlots) \ + PSO_BYPASSED_DIMM_SLOTS, 4, SocketID, ChannelID, ALL_DIMMS, NumberOfBypassedDimmSlots + #define NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel) \ PSO_MAX_CHIPSELS, 4, SocketID, ChannelID, ALL_DIMMS, NumberOfChipSelectsPerChannel @@ -342,6 +362,15 @@ #define MOTHER_BOARD_LAYERS(Layers) \ PSO_MOTHER_BOARD_LAYERS, 4, ANY_SOCKET, ANY_CHANNEL, ALL_DIMMS, Layers +#define ON_DIMM_THERMAL_CONTROL(SocketID, ChannelID, EnableDisable) \ + PSO_ON_DIMM_THERMAL_CONTROL, 4, SocketID, ChannelID, ALL_DIMMS, EnableDisable + +#define DATA_MASK_MB_TYPE(SocketID, ChannelID, DataMaskMbType) \ + PSO_DATA_MASK_MB_TYPE, 4, SocketID, ChannelID, ALL_DIMMS, DataMaskMbType + +#define DQS_ROUTING_TYPE(Type) \ + PSO_DQS_ROUTING_TYPE, 4, ANY_SOCKET, ANY_CHANNEL, ALL_DIMMS, Type + #define MAX_NUMBER_PSO_TABLES 13 /*---------------------------------------------------------------------------------------- * CONDITIONAL OVERRIDE TABLE MACROS diff --git a/src/vendorcode/amd/pi/00670F00/Include/Topology.h b/src/vendorcode/amd/pi/00670F00/Include/Topology.h index 099142eb820e..11f49454d11d 100644 --- a/src/vendorcode/amd/pi/00670F00/Include/Topology.h +++ b/src/vendorcode/amd/pi/00670F00/Include/Topology.h @@ -10,11 +10,11 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: Core - * @e \$Revision: 309090 $ @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $ + * @e \$Revision$ @e \$Date$ */ /***************************************************************************** * - * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc. + * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without |