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| author | Felix Held <felix-coreboot@felixheld.de> | 2023-04-05 19:57:44 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-06-22 13:45:43 +0000 |
| commit | 4c548919c617d7a19482c23156a7546f0e18164f (patch) | |
| tree | 9488f0c0fe0afb10491d484c28cd70347e9459ef /src/vendorcode/amd | |
| parent | 4eee50642ff5ac6e7d7830afd38693943fe17b5b (diff) | |
| download | coreboot-4c548919c617d7a19482c23156a7546f0e18164f.tar.gz coreboot-4c548919c617d7a19482c23156a7546f0e18164f.tar.bz2 coreboot-4c548919c617d7a19482c23156a7546f0e18164f.zip | |
vc/amd/fps/phoenix/platform_descriptors: drop logical-physical mapping
For Phoenix the lane numbers in the DXIO descriptor match the ones in
the schematic, so remove the corresponding text and the table from the
comment on the fsp_dxio_descriptor struct. Since there's no logical to
physical lane number remapping needed for the lanes in the Phoenix DXIO
descriptors, drop the 'logical' from the start_logical_lane and
end_logical_lane fields in the DXIO descriptor and rename those to
start_lane and end_lane.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I94664fd9d3807370b73f9fae8645d444e5faf7b7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74223
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Diffstat (limited to 'src/vendorcode/amd')
| -rw-r--r-- | src/vendorcode/amd/fsp/phoenix/platform_descriptors.h | 15 |
1 files changed, 3 insertions, 12 deletions
diff --git a/src/vendorcode/amd/fsp/phoenix/platform_descriptors.h b/src/vendorcode/amd/fsp/phoenix/platform_descriptors.h index a26013818715..9335aa7cff4a 100644 --- a/src/vendorcode/amd/fsp/phoenix/platform_descriptors.h +++ b/src/vendorcode/amd/fsp/phoenix/platform_descriptors.h @@ -165,16 +165,7 @@ typedef struct __packed { /* * Phoenix DXIO Descriptor: Used for assigning lanes to PCIe engines, configure - * bifurcation and other settings. Beware that the lane numbers in here are the - * logical and not the physical lane numbers! - * - * Phoenix DXIO logical lane to physical PCIe lane mapping: - * - * logical | physical - * ----------|------------ - * PA[00:03] | GPP[03:00] - * PA[04:05] | GPP[08:09] - * PB[00:07] | GPP[12:19] + * bifurcation and other settings. * * Different ports mustn't overlap or be assigned to the same lane(s). Within * ports with the same width the one with a higher start logical lane number @@ -183,8 +174,8 @@ typedef struct __packed { */ typedef struct __packed { uint8_t engine_type; // See dxio_engine_type - uint8_t start_logical_lane; // Start lane of the pci device - uint8_t end_logical_lane; // End lane of the pci device + uint8_t start_lane; // Start lane of the pci device + uint8_t end_lane; // End lane of the pci device uint8_t gpio_group_id; // GPIO number used as reset uint32_t port_present :1; // Should be TRUE if train link uint32_t :7; |