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| author | Paul Menzel <pmenzel@molgen.mpg.de> | 2021-03-05 01:24:41 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-07-12 07:31:52 +0000 |
| commit | 69569e530645e0a984d5134059a6065d9252e8eb (patch) | |
| tree | 90eebf1aeb9abb158b03c3b2e9a31b28f29d3e5c /src/vendorcode/amd | |
| parent | 9c7122f1e8c98390ff81d22f90d64220fca4a393 (diff) | |
| download | coreboot-69569e530645e0a984d5134059a6065d9252e8eb.tar.gz coreboot-69569e530645e0a984d5134059a6065d9252e8eb.tar.bz2 coreboot-69569e530645e0a984d5134059a6065d9252e8eb.zip | |
vc/amd/sb800: SBCMN: Cast to 32-bit before shift
SB800: sb_Before_Pci_Init
shift out of bounds src/vendorcode/amd/cimx/sb800/SBCMN.c:486:57
ubsan: unrecoverable error.
Found-by: UBSAN
Change-Id: Id05b96f1f4cf4a1cf8283db22e10ab8df833406d
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51286
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/vendorcode/amd')
| -rw-r--r-- | src/vendorcode/amd/cimx/sb800/SBCMN.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/vendorcode/amd/cimx/sb800/SBCMN.c b/src/vendorcode/amd/cimx/sb800/SBCMN.c index ab203a111d28..8f1bbf919086 100644 --- a/src/vendorcode/amd/cimx/sb800/SBCMN.c +++ b/src/vendorcode/amd/cimx/sb800/SBCMN.c @@ -417,9 +417,9 @@ commonInitEarlyBoot ( abLinkInitBeforePciEnum (pConfig); // Set ABCFG registers // AB MSI if ( pConfig->BuildParameters.AbMsi) { - abValue = readAlink (SB_ABCFG_REG94 | (UINT32) (ABCFG << 29)); + abValue = readAlink (SB_ABCFG_REG94 | ((UINT32) ABCFG << 29)); abValue = abValue | BIT20; - writeAlink (SB_ABCFG_REG94 | (UINT32) (ABCFG << 29), abValue); + writeAlink (SB_ABCFG_REG94 | ((UINT32) ABCFG << 29), abValue); } @@ -483,12 +483,12 @@ abSpecialSetBeforePciEnum ( ) { UINT32 abValue; - abValue = readAlink (SB_ABCFG_REGC0 | (UINT32) (ABCFG << 29)); + abValue = readAlink (SB_ABCFG_REGC0 | ((UINT32) ABCFG << 29)); abValue &= 0xf0; if ( pConfig->SbPcieOrderRule && abValue ) { - abValue = readAlink (SB_RCINDXC_REG02 | (UINT32) (RCINDXC << 29)); + abValue = readAlink (SB_RCINDXC_REG02 | ((UINT32) RCINDXC << 29)); abValue = abValue | BIT9; - writeAlink (SB_RCINDXC_REG02 | (UINT32) (RCINDXC << 29), abValue); + writeAlink (SB_RCINDXC_REG02 | ((UINT32) RCINDXC << 29), abValue); } } @@ -620,7 +620,7 @@ abLinkInitBeforePciEnum ( pAbTblPtr = (ABTBLENTRY *) FIXUP_PTR (&abTblEntry800[0]); abcfgTbl (pAbTblPtr); if ( cimResetCpuOnSyncFlood ) { - rwAlink (SB_ABCFG_REG10050 | (UINT32) (ABCFG << 29), ~BIT2, BIT2); + rwAlink (SB_ABCFG_REG10050 | ((UINT32) ABCFG << 29), ~BIT2, BIT2); } } |