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| author | Felix Held <felix-coreboot@felixheld.de> | 2023-03-02 16:40:29 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-05-18 16:23:27 +0000 |
| commit | 8c119079d1b9c11c1f9011ecf555a2fc6fd3cc34 (patch) | |
| tree | 8c5e9307beab5ae988834744e5e9a88dd5a62345 /src/vendorcode/amd | |
| parent | 8414eed5a04004a886cafc65763ff5448ff805dd (diff) | |
| download | coreboot-8c119079d1b9c11c1f9011ecf555a2fc6fd3cc34.tar.gz coreboot-8c119079d1b9c11c1f9011ecf555a2fc6fd3cc34.tar.bz2 coreboot-8c119079d1b9c11c1f9011ecf555a2fc6fd3cc34.zip | |
vc/amd/fsp/phoenix/FspUsb: update USB config struct for Phoenix SoC
Phoenix has one more Type C port and two more USB2 ports which are used
as the legacy USB part of the two USB4 ports. The USB struct version
numbers have also changed, since it's a newer and incompatible version
of that struct.
TEST=After changing FSP to not hard-code the USB PHY config, but use the
configuration provided by coreboot, and applying this patch, the USB
connector on the USB2 port 4 lines works.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If52934595dd612154b97e7b90dbd96243146017a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73379
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/vendorcode/amd')
| -rw-r--r-- | src/vendorcode/amd/fsp/phoenix/FspUsb.h | 12 |
1 files changed, 5 insertions, 7 deletions
diff --git a/src/vendorcode/amd/fsp/phoenix/FspUsb.h b/src/vendorcode/amd/fsp/phoenix/FspUsb.h index f7d28bf6a85e..0dcfd714010e 100644 --- a/src/vendorcode/amd/fsp/phoenix/FspUsb.h +++ b/src/vendorcode/amd/fsp/phoenix/FspUsb.h @@ -1,16 +1,14 @@ #ifndef __FSPUSB_H__ #define __FSPUSB_H__ -/* TODO: Update for Phoenix */ - #include <FspUpd.h> -#define FSP_USB_STRUCT_MAJOR_VERSION 0xd -#define FSP_USB_STRUCT_MINOR_VERSION 0xe +#define FSP_USB_STRUCT_MAJOR_VERSION 0xf +#define FSP_USB_STRUCT_MINOR_VERSION 0x1 -#define USB2_PORT_COUNT 6 +#define USB2_PORT_COUNT 8 #define USB3_PORT_COUNT 3 -#define USBC_COMBO_PHY_COUNT 2 +#define USBC_COMBO_PHY_COUNT 3 struct fch_usb2_phy { uint8_t compdistune; ///< COMPDISTUNE @@ -58,7 +56,7 @@ struct usb_phy_config { uint8_t BatteryChargerEnable; ///< bit[1:0]-Usb0 Port[1:0], bit[3:2]-Usb1 Port[1:0] uint8_t PhyP3CpmP4Support; ///< bit[1:0]-Usb0 Port[1:0], bit[3:2]-Usb1 Port[1:0] uint8_t ComboPhyStaticConfig[USBC_COMBO_PHY_COUNT]; ///< 0-Type C, 1- USB only mode, 2- DP only mode, 3- USB + DP - uint8_t Reserved2[4]; + uint8_t Reserved2[3]; } __packed; #endif |