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authorSubrata Banik <subrata.banik@intel.com>2020-08-30 13:51:44 +0530
committerSubrata Banik <subrata.banik@intel.com>2020-09-01 03:06:04 +0000
commit8e6d5f2937c169914e46b5ebc973e5df5e4290a7 (patch)
tree1550c8877877a7a9b197da65bcff76f878bee560 /src/vendorcode/cavium
parentb7a68d5b05259a07a84a546e6a7e40948ba705ac (diff)
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{include,mb,soc,sb,vendorcode}: Make hexadecimal notation consistent
Convert 0X -> 0x Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: Iea3ca67908135d0e85083a05bad2ea176ca34095 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44926 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/vendorcode/cavium')
-rw-r--r--src/vendorcode/cavium/bdk/libbdk-hal/qlm/bdk-qlm-errata-cn8xxx.c6
-rw-r--r--src/vendorcode/cavium/bdk/libdram/dram-init-ddr3.c2
-rw-r--r--src/vendorcode/cavium/include/bdk/libbdk-arch/bdk-csrs-ap.h40
-rw-r--r--src/vendorcode/cavium/include/bdk/libbdk-arch/bdk-csrs-usbdrd.h8
4 files changed, 28 insertions, 28 deletions
diff --git a/src/vendorcode/cavium/bdk/libbdk-hal/qlm/bdk-qlm-errata-cn8xxx.c b/src/vendorcode/cavium/bdk/libbdk-hal/qlm/bdk-qlm-errata-cn8xxx.c
index a7602de7584f..4eeeca3daed7 100644
--- a/src/vendorcode/cavium/bdk/libbdk-hal/qlm/bdk-qlm-errata-cn8xxx.c
+++ b/src/vendorcode/cavium/bdk/libbdk-hal/qlm/bdk-qlm-errata-cn8xxx.c
@@ -166,7 +166,7 @@ int __bdk_qlm_errata_gser_26150(bdk_node_t node, int qlm, int baud_mhz)
Enable Rx power state override */
BDK_CSR_MODIFY(c, node, BDK_GSERX_LANEX_PCS_CTLIFC_2(qlm, i),
c.s.cfg_tx_pstate_req_ovrrd_en = 0x1;
- c.s.cfg_rx_pstate_req_ovrrd_en = 0X1);
+ c.s.cfg_rx_pstate_req_ovrrd_en = 0x1);
/* Step 4: Set GSER()_LANE(lane_n)_PCS_CTLIFC_2[CTLIFC_OVRRD_REQ] = 1
Start the CTLIFC override state machine */
BDK_CSR_MODIFY(c, node, BDK_GSERX_LANEX_PCS_CTLIFC_2(qlm, i),
@@ -200,7 +200,7 @@ int __bdk_qlm_errata_gser_26150(bdk_node_t node, int qlm, int baud_mhz)
Enable Rx power state override */
BDK_CSR_MODIFY(c, node, BDK_GSERX_LANEX_PCS_CTLIFC_2(qlm, i),
c.s.cfg_tx_pstate_req_ovrrd_en = 0x1;
- c.s.cfg_rx_pstate_req_ovrrd_en = 0X1);
+ c.s.cfg_rx_pstate_req_ovrrd_en = 0x1);
/* Step 10: Set GSER()_LANE(lane_n)_PCS_CTLIFC_2[CTLIFC_OVRRD_REQ] = 1
Start the CTLIFC override state machine */
BDK_CSR_MODIFY(c, node, BDK_GSERX_LANEX_PCS_CTLIFC_2(qlm, i),
@@ -219,7 +219,7 @@ int __bdk_qlm_errata_gser_26150(bdk_node_t node, int qlm, int baud_mhz)
Disable Rx power state override */
BDK_CSR_MODIFY(c, node, BDK_GSERX_LANEX_PCS_CTLIFC_2(qlm, i),
c.s.cfg_tx_pstate_req_ovrrd_en = 0x0;
- c.s.cfg_rx_pstate_req_ovrrd_en = 0X0);
+ c.s.cfg_rx_pstate_req_ovrrd_en = 0x0);
}
/* Step 13: Poll GSER()_PLL_STAT.[PLL_LOCK] = 1
Poll and check that PLL is locked */
diff --git a/src/vendorcode/cavium/bdk/libdram/dram-init-ddr3.c b/src/vendorcode/cavium/bdk/libdram/dram-init-ddr3.c
index 306678759df7..92cbe74a011b 100644
--- a/src/vendorcode/cavium/bdk/libdram/dram-init-ddr3.c
+++ b/src/vendorcode/cavium/bdk/libdram/dram-init-ddr3.c
@@ -3148,7 +3148,7 @@ int init_octeon3_ddr3_interface(bdk_node_t node,
bank_bits = (2 + ((spd_banks >> 4) & 0x3)) + ((spd_banks >> 6) & 0x3);
bank_bits = min((int)bank_bits, 4); /* Controller can only address 4 bits. */
- spd_package = 0XFF & read_spd(node, &dimm_config_table[0], DDR4_SPD_PACKAGE_TYPE);
+ spd_package = 0xFF & read_spd(node, &dimm_config_table[0], DDR4_SPD_PACKAGE_TYPE);
if (spd_package & 0x80) { // non-monolithic device
is_stacked_die = (!disable_stacked_die) ? ((spd_package & 0x73) == 0x11) : 0;
ddr_print("DDR4: Package Type 0x%x (%s), %d die\n", spd_package,
diff --git a/src/vendorcode/cavium/include/bdk/libbdk-arch/bdk-csrs-ap.h b/src/vendorcode/cavium/include/bdk/libbdk-arch/bdk-csrs-ap.h
index 20ed3af73749..25887b477cc4 100644
--- a/src/vendorcode/cavium/include/bdk/libbdk-arch/bdk-csrs-ap.h
+++ b/src/vendorcode/cavium/include/bdk/libbdk-arch/bdk-csrs-ap.h
@@ -17483,7 +17483,7 @@ union bdk_ap_id_aa64mmfr0_el1
uint64_t tgran4 : 4; /**< [ 31: 28](RO) Support for 4KB memory translation granule size.
All other values are reserved.
0x0 = 4KB granule supported.
- 0XF = 4KB granule not supported.
+ 0xF = 4KB granule not supported.
In CNXXXX, supported. */
uint64_t tgran64 : 4; /**< [ 27: 24](RO) Support for 64KB memory translation granule size.
@@ -17600,7 +17600,7 @@ union bdk_ap_id_aa64mmfr0_el1
uint64_t tgran4 : 4; /**< [ 31: 28](RO) Support for 4KB memory translation granule size.
All other values are reserved.
0x0 = 4KB granule supported.
- 0XF = 4KB granule not supported.
+ 0xF = 4KB granule not supported.
In CNXXXX, supported. */
uint64_t reserved_32_63 : 32;
@@ -17614,7 +17614,7 @@ union bdk_ap_id_aa64mmfr0_el1
uint64_t tgran4 : 4; /**< [ 31: 28](RO) Support for 4KB memory translation granule size.
All other values are reserved.
0x0 = 4KB granule supported.
- 0XF = 4KB granule not supported.
+ 0xF = 4KB granule not supported.
In CNXXXX, supported. */
uint64_t tgran64 : 4; /**< [ 27: 24](RO) Support for 64KB memory translation granule size.
@@ -17735,7 +17735,7 @@ union bdk_ap_id_aa64mmfr0_el1
uint64_t tgran4 : 4; /**< [ 31: 28](RO) Support for 4KB memory translation granule size.
All other values are reserved.
0x0 = 4KB granule supported.
- 0XF = 4KB granule not supported.
+ 0xF = 4KB granule not supported.
In CNXXXX, supported. */
uint64_t reserved_32_63 : 32;
@@ -23442,14 +23442,14 @@ union bdk_ap_pmceid1_el0
\<pre\>
Bit Event number Event mnemonic
- 24 0X0038 = REMOTE_ACCESS_RD.
- 23 0X0037 = LL_CACHE_MISS_RD.
- 22 0X0036 = LL_CACHE_RD.
- 21 0X0035 = ITLB_WALK.
- 20 0X0034 = DTLB_WALK.
- 19 0X0033 = LL_CACHE MISS.
- 18 0X0032 = LL_CACHE.
- 17 0X0031 = REMOTE_ACCESS.
+ 24 0x0038 = REMOTE_ACCESS_RD.
+ 23 0x0037 = LL_CACHE_MISS_RD.
+ 22 0x0036 = LL_CACHE_RD.
+ 21 0x0035 = ITLB_WALK.
+ 20 0x0034 = DTLB_WALK.
+ 19 0x0033 = LL_CACHE MISS.
+ 18 0x0032 = LL_CACHE.
+ 17 0x0031 = REMOTE_ACCESS.
16 RAZ
15 0x002f = L2D_TLB.
14 0x002e = L2I_TLB_REFILL.
@@ -23474,14 +23474,14 @@ union bdk_ap_pmceid1_el0
\<pre\>
Bit Event number Event mnemonic
- 24 0X0038 = REMOTE_ACCESS_RD.
- 23 0X0037 = LL_CACHE_MISS_RD.
- 22 0X0036 = LL_CACHE_RD.
- 21 0X0035 = ITLB_WALK.
- 20 0X0034 = DTLB_WALK.
- 19 0X0033 = LL_CACHE MISS.
- 18 0X0032 = LL_CACHE.
- 17 0X0031 = REMOTE_ACCESS.
+ 24 0x0038 = REMOTE_ACCESS_RD.
+ 23 0x0037 = LL_CACHE_MISS_RD.
+ 22 0x0036 = LL_CACHE_RD.
+ 21 0x0035 = ITLB_WALK.
+ 20 0x0034 = DTLB_WALK.
+ 19 0x0033 = LL_CACHE MISS.
+ 18 0x0032 = LL_CACHE.
+ 17 0x0031 = REMOTE_ACCESS.
16 RAZ
15 0x002f = L2D_TLB.
14 0x002e = L2I_TLB_REFILL.
diff --git a/src/vendorcode/cavium/include/bdk/libbdk-arch/bdk-csrs-usbdrd.h b/src/vendorcode/cavium/include/bdk/libbdk-arch/bdk-csrs-usbdrd.h
index fc28b58067cc..949a56008f85 100644
--- a/src/vendorcode/cavium/include/bdk/libbdk-arch/bdk-csrs-usbdrd.h
+++ b/src/vendorcode/cavium/include/bdk/libbdk-arch/bdk-csrs-usbdrd.h
@@ -9446,7 +9446,7 @@ union bdk_usbdrdx_uctl_ctl
[REF_SSP_EN] is asserted. */
uint64_t ref_clk_div2 : 1; /**< [ 38: 38](R/W) Divides the reference clock by two before feeding it into the REF_CLK_FSEL divider.
- If [REF_CLK_SEL] = 0x0, 0x1 or 0X2 then the legal values are:
+ If [REF_CLK_SEL] = 0x0, 0x1 or 0x2 then the legal values are:
all DLMC_REF_CLK* frequencies: 0x0 is the only legal value.
If [REF_CLK_SEL] = 0x4, 0x5 or 0x6 then the legal values are:
@@ -9814,7 +9814,7 @@ union bdk_usbdrdx_uctl_ctl
0x07 is the only legal value. */
uint64_t ref_clk_div2 : 1; /**< [ 38: 38](R/W) Divides the reference clock by two before feeding it into the REF_CLK_FSEL divider.
- If [REF_CLK_SEL] = 0x0, 0x1 or 0X2 then the legal values are:
+ If [REF_CLK_SEL] = 0x0, 0x1 or 0x2 then the legal values are:
all DLMC_REF_CLK* frequencies: 0x0 is the only legal value.
If [REF_CLK_SEL] = 0x4, 0x5 or 0x6 then the legal values are:
@@ -10106,7 +10106,7 @@ union bdk_usbdrdx_uctl_ctl
[REF_SSP_EN] is asserted. */
uint64_t ref_clk_div2 : 1; /**< [ 38: 38](R/W) Divides the reference clock by two before feeding it into the REF_CLK_FSEL divider.
- If [REF_CLK_SEL] = 0x0, 0x1 or 0X2 then the legal values are:
+ If [REF_CLK_SEL] = 0x0, 0x1 or 0x2 then the legal values are:
all DLMC_REF_CLK* frequencies: 0x0 is the only legal value.
If [REF_CLK_SEL] = 0x4, 0x5 or 0x6 then the legal values are:
@@ -10458,7 +10458,7 @@ union bdk_usbdrdx_uctl_ctl
0x07 is the only legal value. */
uint64_t ref_clk_div2 : 1; /**< [ 38: 38](R/W) Divides the reference clock by two before feeding it into the REF_CLK_FSEL divider.
- If [REF_CLK_SEL] = 0x0, 0x1 or 0X2 then the legal values are:
+ If [REF_CLK_SEL] = 0x0, 0x1 or 0x2 then the legal values are:
all DLMC_REF_CLK* frequencies: 0x0 is the only legal value.
If [REF_CLK_SEL] = 0x4, 0x5 or 0x6 then the legal values are:
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-05 20:35:32 +0000