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| author | Jonathan Zhang <jonzhang@fb.com> | 2020-06-09 17:56:53 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-06-25 11:57:06 +0000 |
| commit | 6d27778973edf6bdebfa812eac8893d52961a891 (patch) | |
| tree | 8023f5c4d98247b5ef3ceb18b8820e1131753f7e /src/vendorcode/intel/edk2/edk2-stable202005/IntelFsp2Pkg/Include/Ppi/FspmArchConfigPpi.h | |
| parent | c9222f956763d20397152a44985bdb4abdb19e2d (diff) | |
| download | coreboot-6d27778973edf6bdebfa812eac8893d52961a891.tar.gz coreboot-6d27778973edf6bdebfa812eac8893d52961a891.tar.bz2 coreboot-6d27778973edf6bdebfa812eac8893d52961a891.zip | |
vendorcode/intel: Add edk2-stable202005 support
This patch includes (edk2/edk2-stable202005) all required headers
for edk2-stable202005 quarterly EDK2 tag from EDK2 github project
using below command:
>> git clone https://github.com/tianocore/edk2.git vedk2-stable202005
Only include necessary header files.
MdePkg/Include/Base.h was updated to avoid compilation errors through
safeguarding definitions for MIN, MAX, NULL, ABS, ARRAY_SIZE.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I3172505d9b829647ee1208c87623172f10b39310
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42239
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/vendorcode/intel/edk2/edk2-stable202005/IntelFsp2Pkg/Include/Ppi/FspmArchConfigPpi.h')
| -rw-r--r-- | src/vendorcode/intel/edk2/edk2-stable202005/IntelFsp2Pkg/Include/Ppi/FspmArchConfigPpi.h | 47 |
1 files changed, 47 insertions, 0 deletions
diff --git a/src/vendorcode/intel/edk2/edk2-stable202005/IntelFsp2Pkg/Include/Ppi/FspmArchConfigPpi.h b/src/vendorcode/intel/edk2/edk2-stable202005/IntelFsp2Pkg/Include/Ppi/FspmArchConfigPpi.h new file mode 100644 index 000000000000..e3c62a9483c9 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202005/IntelFsp2Pkg/Include/Ppi/FspmArchConfigPpi.h @@ -0,0 +1,47 @@ +/** @file + Header file for FSP-M Arch Config PPI for Dispatch mode + + Copyright (c) 2019, Intel Corporation. All rights reserved.<BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _FSPM_ARCH_CONFIG_PPI_H_ +#define _FSPM_ARCH_CONFIG_PPI_H_ + +#define FSPM_ARCH_CONFIG_PPI_REVISION 0x1 + +/// +/// Global ID for the FSPM_ARCH_CONFIG_PPI. +/// +#define FSPM_ARCH_CONFIG_GUID \ + { \ + 0x824d5a3a, 0xaf92, 0x4c0c, { 0x9f, 0x19, 0x19, 0x52, 0x6d, 0xca, 0x4a, 0xbb } \ + } + +/// +/// This PPI provides FSP-M Arch Config PPI. +/// +typedef struct { + /// + /// Revision of the structure + /// + UINT8 Revision; + UINT8 Reserved[3]; + /// + /// Pointer to the non-volatile storage (NVS) data buffer. + /// If it is NULL it indicates the NVS data is not available. + /// + VOID *NvsBufferPtr; + /// + /// Size of memory to be reserved by FSP below "top + /// of low usable memory" for bootloader usage. + /// + UINT32 BootLoaderTolumSize; + UINT8 Reserved1[4]; +} FSPM_ARCH_CONFIG_PPI; + +extern EFI_GUID gFspmArchConfigPpiGuid; + +#endif // _FSPM_ARCH_CONFIG_PPI_H_ |