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| author | Subrata Banik <subrata.banik@intel.com> | 2020-09-09 12:59:24 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2020-09-10 05:27:03 +0000 |
| commit | 2ee4c0d7f4f39b1eed53e4f6770879c76a2d6eab (patch) | |
| tree | b27a9466f39d2de114cf9aa1d65312b0c744d459 /src/vendorcode/intel/fsp/fsp2_0/alderlake | |
| parent | fed1a1a8b00273d707b8512d59f12f0b48fbc7c9 (diff) | |
| download | coreboot-2ee4c0d7f4f39b1eed53e4f6770879c76a2d6eab.tar.gz coreboot-2ee4c0d7f4f39b1eed53e4f6770879c76a2d6eab.tar.bz2 coreboot-2ee4c0d7f4f39b1eed53e4f6770879c76a2d6eab.zip | |
vendorcode/intel/fsp/alderlake: Fix FSPS_ARCH_UPD redefinition issue
FSPS_ARCH_UPD struct is part of edk2-stable202005 branch (FspApi.h)
hence local definition of FSPS_ARCH_UPD inside FspsUpd.h is causing
compilation issue.
Change-Id: Id5b3637d9ab6d87aab6da810f9c83d3258900a29
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Diffstat (limited to 'src/vendorcode/intel/fsp/fsp2_0/alderlake')
| -rw-r--r-- | src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h | 30 |
1 files changed, 0 insertions, 30 deletions
diff --git a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h index 39c360ddd69b..7ec577a7b5f5 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h @@ -80,36 +80,6 @@ typedef struct { #define SI_PCH_MAX_DEVICE_INTERRUPT_CONFIG 64 ///< Number of all PCH devices
-
-/** FSPS_ARCH_UPD
-**/
-typedef struct {
-
-/** Offset 0x0020 - Reserved
-**/
- UINT8 Revision;
-
-/** Offset 0x0021 - Reserved
-**/
- UINT8 Reserved[3];
-
-/** Offset 0x0024 - Reserved
-**/
- UINT32 Length;
-
-/** Offset 0x0028 - Reserved
-**/
- UINT32 FspEventHandler;
-
-/** Offset 0x002C - Reserved
-**/
- UINT8 EnableMultiPhaseSiliconInit;
-
-/** Offset 0x002D - Reserved
-**/
- UINT8 Reserved1[19];
-} FSPS_ARCH_UPD;
-
/** Fsp S Configuration
**/
typedef struct {
|