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| author | Ronak Kanabar <ronak.kanabar@intel.com> | 2021-09-24 15:40:28 +0530 |
|---|---|---|
| committer | Nick Vaccaro <nvaccaro@google.com> | 2021-09-28 16:38:44 +0000 |
| commit | d326e44959394b06d3c5a595379463a5e621eab9 (patch) | |
| tree | afebee907e33bf4768fe73350908ee7b8c6ad9fe /src/vendorcode/intel/fsp/fsp2_0/alderlake | |
| parent | 3da6528c528456bf9a82060bb5a6b5ff8efc8dd1 (diff) | |
| download | coreboot-d326e44959394b06d3c5a595379463a5e621eab9.tar.gz coreboot-d326e44959394b06d3c5a595379463a5e621eab9.tar.bz2 coreboot-d326e44959394b06d3c5a595379463a5e621eab9.zip | |
vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2374_01
The headers added are generated as per FSP v2374_01.
Previous FSP version was v2347_00.
Changes Include:
- Offset change in FspmUpd.h and FspsUpd.h
BUG=b:201239436
BRANCH=None
TEST=Build and boot brya
Cq-Depend: chrome-internal:4150766
Change-Id: I097e854bcb4033bdaf2498fb97b255e87d3dd70f
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57920
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/vendorcode/intel/fsp/fsp2_0/alderlake')
| -rw-r--r-- | src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h | 8 | ||||
| -rw-r--r-- | src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h | 8 |
2 files changed, 8 insertions, 8 deletions
diff --git a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h index 4ab722cb84d1..9e1a414f4853 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h @@ -3162,7 +3162,7 @@ typedef struct { /** Offset 0x0AA8 - Reserved **/ - UINT8 Reserved46[64]; + UINT8 Reserved46[104]; } FSP_M_CONFIG; /** Fsp M UPD Configuration @@ -3181,11 +3181,11 @@ typedef struct { **/ FSP_M_CONFIG FspmConfig; -/** Offset 0x0AE8 +/** Offset 0x0B10 **/ - UINT8 UnusedUpdSpace29[6]; + UINT8 UnusedUpdSpace31[6]; -/** Offset 0x0AEE +/** Offset 0x0B16 **/ UINT16 UpdTerminator; } FSPM_UPD; diff --git a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h index 14127fce54f5..ddf6ca87ff1c 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h @@ -3869,7 +3869,7 @@ typedef struct { /** Offset 0x0FD5 - Reserved **/ - UINT8 Reserved56[11]; + UINT8 Reserved56[19]; } FSP_S_CONFIG; /** Fsp S UPD Configuration @@ -3888,11 +3888,11 @@ typedef struct { **/ FSP_S_CONFIG FspsConfig; -/** Offset 0x0FE0 +/** Offset 0x0FE8 **/ - UINT8 UnusedUpdSpace40[6]; + UINT8 UnusedUpdSpace42[6]; -/** Offset 0x0FE6 +/** Offset 0x0FEE **/ UINT16 UpdTerminator; } FSPS_UPD; |