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| author | Sean Rhodes <sean@starlabs.systems> | 2023-04-14 11:36:38 +0100 |
|---|---|---|
| committer | Lean Sheng Tan <sheng.tan@9elements.com> | 2023-05-23 08:26:13 +0000 |
| commit | 34a63f3df01c74b7a82ecf43c823e99b52bdedb5 (patch) | |
| tree | a7ad11d26997d2e497947a907d723e11dd792c9a /src/vendorcode/intel/fsp/fsp2_0 | |
| parent | 6c42d14d45974fa5a1b08bbd3c48d8fa7945c4ee (diff) | |
| download | coreboot-34a63f3df01c74b7a82ecf43c823e99b52bdedb5.tar.gz coreboot-34a63f3df01c74b7a82ecf43c823e99b52bdedb5.tar.bz2 coreboot-34a63f3df01c74b7a82ecf43c823e99b52bdedb5.zip | |
mb/starlabs/starbook: Add ramtop to CMOS layout
Add `ramtop` to CMOS layout so SOC_INTEL_COMMON_BASECODE_RAMTOP
can be used.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I88128d2c62bdc3246a3f30e768c353f0fe3faeb7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74432
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Diffstat (limited to 'src/vendorcode/intel/fsp/fsp2_0')
0 files changed, 0 insertions, 0 deletions