diff options
| author | Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> | 2022-06-01 15:11:36 -0700 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2022-06-23 05:00:35 +0000 |
| commit | b2d9d57103a13f89538df41dc4e8fe9dcdb8a967 (patch) | |
| tree | 92c3d087cfa672c7b5fcbcb2c966dd1f83eafd61 /src/vendorcode/intel | |
| parent | e0526fe02330d4296ececb1b81565b3aef28a129 (diff) | |
| download | coreboot-b2d9d57103a13f89538df41dc4e8fe9dcdb8a967.tar.gz coreboot-b2d9d57103a13f89538df41dc4e8fe9dcdb8a967.tar.bz2 coreboot-b2d9d57103a13f89538df41dc4e8fe9dcdb8a967.zip | |
vc/intel/fsp/mtl: Update header files from 2173_00 to 2222_01 for MTL
Update header files for FSP for Meteor Lake platform to version 2222_01, previous version being 2173_00.
FSPM:
Includes below 2 UPDs
1. TdcEnable
2. TdcTimeWindow
FSPS:
Address Offset changes.
BUG=b:234701164
TEST=util/abuild/abuild -p none -t google/rex -a -c max
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I529118c35fa9f851ee2b5f23712ac70e2a5b53c5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64878
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Diffstat (limited to 'src/vendorcode/intel')
| -rw-r--r-- | src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h | 1835 | ||||
| -rw-r--r-- | src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspsUpd.h | 643 |
2 files changed, 1270 insertions, 1208 deletions
diff --git a/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h index 5f0de35a245b..5c1029e8af21 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h @@ -332,52 +332,48 @@ typedef struct { /** Offset 0x014E - Reserved **/ - UINT8 Reserved13; + UINT16 Reserved13; -/** Offset 0x014F - Reserved +/** Offset 0x0150 - Reserved **/ - UINT8 Reserved14; + UINT16 Reserved14; -/** Offset 0x0150 - Reserved +/** Offset 0x0152 - Reserved **/ UINT8 Reserved15; -/** Offset 0x0151 - Reserved +/** Offset 0x0153 - Reserved **/ UINT8 Reserved16; -/** Offset 0x0152 - Reserved +/** Offset 0x0154 - Reserved **/ - UINT8 Reserved17; + UINT16 Reserved17; -/** Offset 0x0153 - Reserved +/** Offset 0x0156 - Reserved **/ - UINT8 Reserved18; + UINT16 Reserved18; -/** Offset 0x0154 - Reserved +/** Offset 0x0158 - Reserved **/ UINT8 Reserved19; -/** Offset 0x0155 - Reserved +/** Offset 0x0159 - Reserved **/ UINT8 Reserved20; -/** Offset 0x0156 - Reserved +/** Offset 0x015A - Reserved **/ UINT8 Reserved21; -/** Offset 0x0157 - Reserved +/** Offset 0x015B - Reserved **/ UINT8 Reserved22; -/** Offset 0x0158 - Reserved +/** Offset 0x015C - Reserved **/ UINT8 Reserved23[2]; -/** Offset 0x015A - Reserved -**/ - UINT8 Reserved24[4]; - /** Offset 0x015E - State of X2APIC_OPT_OUT bit in the DMAR table 0=Disable/Clear, 1=Enable/Set $EN_DIS @@ -386,7 +382,7 @@ typedef struct { /** Offset 0x015F - Reserved **/ - UINT8 Reserved25; + UINT8 Reserved24; /** Offset 0x0160 - Base addresses for VT-d function MMIO access Base addresses for VT-d MMIO access per VT-d engine @@ -401,11 +397,11 @@ typedef struct { /** Offset 0x0185 - Reserved **/ - UINT8 Reserved26; + UINT8 Reserved25; /** Offset 0x0186 - Reserved **/ - UINT8 Reserved27; + UINT8 Reserved26; /** Offset 0x0187 - Internal Graphics Pre-allocated Memory Size of memory preallocated for internal graphics. @@ -430,11 +426,11 @@ typedef struct { /** Offset 0x018A - Reserved **/ - UINT8 Reserved28; + UINT8 Reserved27; /** Offset 0x018B - Reserved **/ - UINT8 Reserved29; + UINT8 Reserved28; /** Offset 0x018C - DDR Frequency Limit Maximum Memory Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867, @@ -451,15 +447,15 @@ typedef struct { /** Offset 0x018F - Reserved **/ - UINT8 Reserved30; + UINT8 Reserved29; /** Offset 0x0190 - Reserved **/ - UINT8 Reserved31; + UINT8 Reserved30; /** Offset 0x0191 - Reserved **/ - UINT8 Reserved32; + UINT8 Reserved31; /** Offset 0x0192 - Controller 0 Channel 0 DIMM Control Enable / Disable DIMMs on Controller 0 Channel 0 @@ -511,19 +507,19 @@ typedef struct { /** Offset 0x019A - Reserved **/ - UINT8 Reserved33; + UINT8 Reserved32; /** Offset 0x019B - Reserved **/ - UINT8 Reserved34; + UINT8 Reserved33; /** Offset 0x019C - Reserved **/ - UINT8 Reserved35; + UINT8 Reserved34; /** Offset 0x019D - Reserved **/ - UINT8 Reserved36; + UINT8 Reserved35; /** Offset 0x019E - Memory Reference Clock 100MHz, 133MHz. @@ -533,107 +529,107 @@ typedef struct { /** Offset 0x019F - Reserved **/ - UINT8 Reserved37; + UINT8 Reserved36; /** Offset 0x01A0 - Reserved **/ - UINT16 Reserved38; + UINT16 Reserved37; /** Offset 0x01A2 - Reserved **/ - UINT16 Reserved39; + UINT16 Reserved38; /** Offset 0x01A4 - Reserved **/ - UINT16 Reserved40; + UINT16 Reserved39; /** Offset 0x01A6 - Reserved **/ - UINT16 Reserved41; + UINT16 Reserved40; /** Offset 0x01A8 - Reserved **/ - UINT8 Reserved42; + UINT8 Reserved41; /** Offset 0x01A9 - Reserved **/ - UINT8 Reserved43; + UINT8 Reserved42; /** Offset 0x01AA - Reserved **/ - UINT16 Reserved44; + UINT16 Reserved43; /** Offset 0x01AC - Reserved **/ - UINT16 Reserved45; + UINT16 Reserved44; /** Offset 0x01AE - Reserved **/ - UINT8 Reserved46; + UINT8 Reserved45; /** Offset 0x01AF - Reserved **/ - UINT8 Reserved47; + UINT8 Reserved46; /** Offset 0x01B0 - Reserved **/ - UINT16 Reserved48; + UINT16 Reserved47; /** Offset 0x01B2 - Reserved **/ - UINT16 Reserved49; + UINT16 Reserved48; /** Offset 0x01B4 - Reserved **/ - UINT8 Reserved50; + UINT8 Reserved49; /** Offset 0x01B5 - Reserved **/ - UINT8 Reserved51; + UINT8 Reserved50; /** Offset 0x01B6 - Reserved **/ - UINT8 Reserved52; + UINT8 Reserved51; /** Offset 0x01B7 - Reserved **/ - UINT8 Reserved53; + UINT8 Reserved52; /** Offset 0x01B8 - Reserved **/ - UINT16 Reserved54; + UINT16 Reserved53; /** Offset 0x01BA - Reserved **/ - UINT16 Reserved55; + UINT16 Reserved54; /** Offset 0x01BC - Reserved **/ - UINT16 Reserved56; + UINT16 Reserved55; /** Offset 0x01BE - Reserved **/ - UINT8 Reserved57; + UINT8 Reserved56; /** Offset 0x01BF - Reserved **/ - UINT8 Reserved58; + UINT8 Reserved57; /** Offset 0x01C0 - Reserved **/ - UINT8 Reserved59; + UINT8 Reserved58; /** Offset 0x01C1 - Reserved **/ - UINT8 Reserved60; + UINT8 Reserved59; /** Offset 0x01C2 - Reserved **/ - UINT8 Reserved61; + UINT8 Reserved60; /** Offset 0x01C3 - Reserved **/ - UINT8 Reserved62; + UINT8 Reserved61; /** Offset 0x01C4 - Enable Intel HD Audio (Azalia) 0: Disable, 1: Enable (Default) Azalia controller @@ -649,91 +645,91 @@ typedef struct { /** Offset 0x01C6 - Reserved **/ - UINT8 Reserved63[4]; + UINT8 Reserved62[4]; /** Offset 0x01CA - Reserved **/ - UINT16 Reserved64[4]; + UINT16 Reserved63[4]; /** Offset 0x01D2 - Reserved **/ - UINT8 Reserved65; + UINT8 Reserved64; /** Offset 0x01D3 - Reserved **/ - UINT8 Reserved66; + UINT8 Reserved65; /** Offset 0x01D4 - Reserved **/ - UINT8 Reserved67; + UINT8 Reserved66; /** Offset 0x01D5 - Reserved **/ - UINT8 Reserved68; + UINT8 Reserved67; /** Offset 0x01D6 - Reserved **/ - UINT16 Reserved69; + UINT16 Reserved68; /** Offset 0x01D8 - Reserved **/ - UINT8 Reserved70; + UINT8 Reserved69; /** Offset 0x01D9 - Reserved **/ - UINT8 Reserved71[3]; + UINT8 Reserved70[3]; /** Offset 0x01DC - Reserved **/ - UINT32 Reserved72; + UINT32 Reserved71; /** Offset 0x01E0 - Reserved **/ - UINT32 Reserved73; + UINT32 Reserved72; /** Offset 0x01E4 - Reserved **/ - UINT8 Reserved74; + UINT8 Reserved73; /** Offset 0x01E5 - Reserved **/ - UINT8 Reserved75; + UINT8 Reserved74; /** Offset 0x01E6 - Reserved **/ - UINT8 Reserved76; + UINT8 Reserved75; /** Offset 0x01E7 - Reserved **/ - UINT8 Reserved77; + UINT8 Reserved76; /** Offset 0x01E8 - Reserved **/ - UINT16 Reserved78; + UINT16 Reserved77; /** Offset 0x01EA - Reserved **/ - UINT16 Reserved79; + UINT16 Reserved78; /** Offset 0x01EC - Reserved **/ - UINT16 Reserved80; + UINT16 Reserved79; /** Offset 0x01EE - Reserved **/ - UINT16 Reserved81; + UINT16 Reserved80; /** Offset 0x01F0 - Reserved **/ - UINT8 Reserved82; + UINT8 Reserved81; /** Offset 0x01F1 - Reserved **/ - UINT8 Reserved83; + UINT8 Reserved82; /** Offset 0x01F2 - Reserved **/ - UINT8 Reserved84; + UINT8 Reserved83; /** Offset 0x01F3 - Enable/Disable SA IPU Enable(Default): Enable SA IPU, Disable: Disable SA IPU @@ -845,47 +841,47 @@ typedef struct { /** Offset 0x020A - Reserved **/ - UINT8 Reserved85[6]; + UINT8 Reserved84[6]; /** Offset 0x0210 - Reserved **/ - UINT64 Reserved86; + UINT64 Reserved85; /** Offset 0x0218 - Reserved **/ - UINT16 Reserved87; + UINT16 Reserved86; /** Offset 0x021A - Reserved **/ - UINT8 Reserved88; + UINT8 Reserved87; /** Offset 0x021B - Reserved **/ - UINT8 Reserved89; + UINT8 Reserved88; /** Offset 0x021C - Reserved **/ - UINT8 Reserved90; + UINT8 Reserved89; /** Offset 0x021D - Reserved **/ - UINT8 Reserved91[113]; + UINT8 Reserved90[113]; /** Offset 0x028E - Reserved **/ - UINT8 Reserved92; + UINT8 Reserved91; /** Offset 0x028F - Reserved **/ - UINT8 Reserved93; + UINT8 Reserved92; /** Offset 0x0290 - Reserved **/ - UINT8 Reserved94; + UINT8 Reserved93; /** Offset 0x0291 - Reserved **/ - UINT8 Reserved95; + UINT8 Reserved94; /** Offset 0x0292 - DMI Gen3 Root port preset values per lane Used for programming DMI Gen3 preset values per lane. Range: 0-9, 4 is default for each lane @@ -894,187 +890,183 @@ typedef struct { /** Offset 0x029A - Reserved **/ - UINT8 Reserved96[8]; + UINT8 Reserved95[8]; /** Offset 0x02A2 - Reserved **/ - UINT8 Reserved97[8]; + UINT8 Reserved96[8]; /** Offset 0x02AA - Reserved **/ - UINT8 Reserved98; + UINT8 Reserved97; /** Offset 0x02AB - Reserved **/ - UINT8 Reserved99; + UINT8 Reserved98; /** Offset 0x02AC - Reserved **/ - UINT8 Reserved100; + UINT8 Reserved99; /** Offset 0x02AD - Reserved **/ - UINT8 Reserved101; + UINT8 Reserved100; /** Offset 0x02AE - Reserved **/ - UINT8 Reserved102; + UINT8 Reserved101; /** Offset 0x02AF - Reserved **/ - UINT8 Reserved103; + UINT8 Reserved102; /** Offset 0x02B0 - Reserved **/ - UINT8 Reserved104[8]; + UINT8 Reserved103[8]; /** Offset 0x02B8 - Reserved **/ - UINT8 Reserved105[8]; + UINT8 Reserved104[8]; /** Offset 0x02C0 - Reserved **/ - UINT8 Reserved106[8]; + UINT8 Reserved105[8]; /** Offset 0x02C8 - Reserved **/ - UINT8 Reserved107[8]; + UINT8 Reserved106[8]; /** Offset 0x02D0 - Reserved **/ - UINT8 Reserved108; + UINT8 Reserved107; /** Offset 0x02D1 - Reserved **/ - UINT8 Reserved109[8]; + UINT8 Reserved108[8]; /** Offset 0x02D9 - Reserved **/ - UINT8 Reserved110[8]; + UINT8 Reserved109[8]; /** Offset 0x02E1 - Reserved **/ - UINT8 Reserved111; + UINT8 Reserved110; /** Offset 0x02E2 - Reserved **/ - UINT8 Reserved112[8]; + UINT8 Reserved111[8]; /** Offset 0x02EA - Reserved **/ - UINT8 Reserved113[8]; + UINT8 Reserved112[8]; /** Offset 0x02F2 - Reserved **/ - UINT8 Reserved114[8]; + UINT8 Reserved113[8]; /** Offset 0x02FA - Reserved **/ - UINT8 Reserved115[8]; + UINT8 Reserved114[8]; /** Offset 0x0302 - Reserved **/ - UINT8 Reserved116; + UINT8 Reserved115; /** Offset 0x0303 - Reserved **/ - UINT8 Reserved117; + UINT8 Reserved116; /** Offset 0x0304 - Reserved **/ - UINT8 Reserved118; + UINT8 Reserved117; /** Offset 0x0305 - Reserved **/ - UINT8 Reserved119[8]; + UINT8 Reserved118[8]; /** Offset 0x030D - Reserved **/ - UINT8 Reserved120; + UINT8 Reserved119; /** Offset 0x030E - Reserved **/ - UINT8 Reserved121; + UINT8 Reserved120; /** Offset 0x030F - Reserved **/ - UINT8 Reserved122[8]; + UINT8 Reserved121[8]; /** Offset 0x0317 - Reserved **/ - UINT8 Reserved123[8]; + UINT8 Reserved122[8]; /** Offset 0x031F - Reserved **/ - UINT8 Reserved124; + UINT8 Reserved123; /** Offset 0x0320 - Reserved **/ - UINT8 Reserved125[8]; + UINT8 Reserved124[8]; /** Offset 0x0328 - Reserved **/ - UINT8 Reserved126; + UINT8 Reserved125; /** Offset 0x0329 - Reserved **/ - UINT8 Reserved127[3]; + UINT8 Reserved126[3]; /** Offset 0x032C - Reserved **/ - UINT32 Reserved128; + UINT32 Reserved127; /** Offset 0x0330 - Reserved **/ - UINT32 Reserved129; + UINT32 Reserved128; /** Offset 0x0334 - Reserved **/ - UINT32 Reserved130; + UINT32 Reserved129; /** Offset 0x0338 - Reserved **/ - UINT32 Reserved131; + UINT32 Reserved130; /** Offset 0x033C - Reserved **/ - UINT16 Reserved132; + UINT16 Reserved131; /** Offset 0x033E - Reserved **/ - UINT16 Reserved133; + UINT16 Reserved132; /** Offset 0x0340 - Reserved **/ - UINT32 Reserved134; + UINT32 Reserved133; /** Offset 0x0344 - Reserved **/ - UINT32 Reserved135; + UINT32 Reserved134; /** Offset 0x0348 - Reserved **/ - UINT32 Reserved136; + UINT32 Reserved135; /** Offset 0x034C - Reserved **/ - UINT32 Reserved137; + UINT32 Reserved136; /** Offset 0x0350 - Reserved **/ - UINT8 Reserved138; + UINT8 Reserved137; /** Offset 0x0351 - Reserved **/ - UINT8 Reserved139; + UINT8 Reserved138; -/** Offset 0x0352 - C6DRAM power gating feature - This policy indicates whether or not BIOS should allocate PRMRR memory for C6DRAM - power gating feature.- 0: Don't allocate any PRMRR memory for C6DRAM power gating - feature.- <b>1: Allocate PRMRR memory for C6DRAM power gating feature</b>. - $EN_DIS +/** Offset 0x0352 - Reserved **/ - UINT8 EnableC6Dram; + UINT8 Reserved139; /** Offset 0x0353 - Reserved **/ @@ -1092,46 +1084,48 @@ typedef struct { **/ UINT8 Reserved143; -/** Offset 0x0357 - Reserved -**/ - UINT8 Reserved144; - -/** Offset 0x0358 - Hyper Threading Enable/Disable - Enable or Disable Hyper Threading; 0: Disable; <b>1: Enable</b> +/** Offset 0x0357 - Hyper Threading Enable/Disable + Enable or Disable Hyper-Threading Technology. 0: Disable; <b>1: Enable</b> $EN_DIS **/ UINT8 HyperThreading; -/** Offset 0x0359 - Reserved +/** Offset 0x0358 - Reserved **/ - UINT8 Reserved145; + UINT8 Reserved144; -/** Offset 0x035A - CPU ratio value - CPU ratio value. Valid Range 0 to 63 +/** Offset 0x0359 - CPU ratio value + This value must be between Max Efficiency Ratio (LFM) and Maximum non-turbo ratio + set by Hardware (HFM). Valid Range 0 to 63. **/ UINT8 CpuRatio; -/** Offset 0x035B - Reserved +/** Offset 0x035A - Reserved **/ - UINT8 Reserved146; + UINT8 Reserved145; -/** Offset 0x035C - Reserved +/** Offset 0x035B - Reserved **/ - UINT8 Reserved147; + UINT8 Reserved146; -/** Offset 0x035D - Processor Early Power On Configuration FCLK setting - <b>0: 800 MHz (ULT/ULX)</b>. <b>1: 1 GHz (DT/Halo)</b>. Not supported on ULT/ULX.- - 2: 400 MHz. - 3: Reserved +/** Offset 0x035C - Processor Early Power On Configuration FCLK setting + FCLK frequency can take values of 400MHz, 800MHz and 1GHz. <b>0: 800 MHz (ULT/ULX)</b>. + <b>1: 1 GHz (DT/Halo)</b>. Not supported on ULT/ULX.- 2: 400 MHz. - 3: Reserved 0:800 MHz, 1: 1 GHz, 2: 400 MHz, 3: Reserved **/ UINT8 FClkFrequency; -/** Offset 0x035E - Enable or Disable VMX - Enable or Disable VMX; 0: Disable; <b>1: Enable</b>. +/** Offset 0x035D - Enable or Disable VMX + Enable or Disable VMX, When enabled, a VMM can utilize the additional hardware capabilities + provided by Vanderpool Technology. 0: Disable; <b>1: Enable</b>. $EN_DIS **/ UINT8 VmxEnable; +/** Offset 0x035E - Reserved +**/ + UINT8 Reserved147; + /** Offset 0x035F - Reserved **/ UINT8 Reserved148; @@ -1185,7 +1179,8 @@ typedef struct { UINT16 Reserved160; /** Offset 0x0372 - Enable or Disable TME - Enable or Disable TME; <b>0: Disable</b>; 1: Enable. + Configure Total Memory Encryption (TME) to protect DRAM data from physical attacks. + <b>0: Disable</b>; 1: Enable. $EN_DIS **/ UINT8 TmeEnable; @@ -1222,1826 +1217,1872 @@ typedef struct { /** Offset 0x0384 - Reserved **/ - UINT8 Reserved167; + UINT8 Reserved167[4]; -/** Offset 0x0385 - Reserved +/** Offset 0x0388 - Reserved **/ - UINT8 Reserved168; + UINT16 Reserved168[4]; -/** Offset 0x0386 - Reserved +/** Offset 0x0390 - Reserved **/ - UINT16 Reserved169[15]; + UINT16 Reserved169[4]; -/** Offset 0x03A4 - Reserved +/** Offset 0x0398 - Reserved **/ - UINT8 Reserved170[15]; + UINT8 Reserved170; -/** Offset 0x03B3 - Reserved +/** Offset 0x0399 - Reserved **/ - UINT8 Reserved171[15]; + UINT8 Reserved171; -/** Offset 0x03C2 - Reserved +/** Offset 0x039A - Reserved **/ - UINT8 Reserved172; + UINT16 Reserved172[15]; -/** Offset 0x03C3 - Reserved +/** Offset 0x03B8 - Reserved **/ - UINT8 Reserved173; + UINT8 Reserved173[15]; -/** Offset 0x03C4 - Reserved +/** Offset 0x03C7 - Reserved **/ - UINT16 Reserved174[8]; + UINT8 Reserved174[15]; -/** Offset 0x03D4 - Reserved +/** Offset 0x03D6 - Reserved **/ - UINT8 Reserved175[8]; + UINT8 Reserved175; -/** Offset 0x03DC - Reserved +/** Offset 0x03D7 - Reserved **/ UINT8 Reserved176; -/** Offset 0x03DD - Reserved +/** Offset 0x03D8 - Reserved **/ - UINT8 Reserved177[8]; + UINT16 Reserved177[8]; -/** Offset 0x03E5 - Reserved +/** Offset 0x03E8 - Reserved **/ - UINT8 Reserved178; + UINT8 Reserved178[8]; -/** Offset 0x03E6 - Reserved +/** Offset 0x03F0 - Reserved **/ - UINT16 Reserved179; + UINT8 Reserved179; -/** Offset 0x03E8 - Reserved +/** Offset 0x03F1 - Reserved **/ - UINT8 Reserved180[4]; + UINT8 Reserved180[8]; -/** Offset 0x03EC - Reserved +/** Offset 0x03F9 - Reserved **/ - UINT8 Reserved181; + UINT8 Reserved181[1]; -/** Offset 0x03ED - Reserved +/** Offset 0x03FA - Reserved **/ - UINT8 Reserved182; + UINT16 Reserved182[8]; -/** Offset 0x03EE - Reserved +/** Offset 0x040A - Reserved **/ - UINT8 Reserved183; + UINT16 Reserved183[8]; -/** Offset 0x03EF - Reserved +/** Offset 0x041A - Reserved **/ - UINT8 Reserved184; + UINT8 Reserved184[8]; -/** Offset 0x03F0 - Reserved +/** Offset 0x0422 - Reserved **/ UINT8 Reserved185; -/** Offset 0x03F1 - Reserved +/** Offset 0x0423 - Reserved **/ UINT8 Reserved186; -/** Offset 0x03F2 - Reserved +/** Offset 0x0424 - Reserved **/ - UINT16 Reserved187[15]; + UINT16 Reserved187; -/** Offset 0x0410 - Reserved +/** Offset 0x0426 - Reserved **/ - UINT8 Reserved188[15]; + UINT8 Reserved188[4]; -/** Offset 0x041F - Reserved +/** Offset 0x042A - Reserved **/ - UINT8 Reserved189[15]; + UINT8 Reserved189; -/** Offset 0x042E - Reserved +/** Offset 0x042B - Reserved **/ UINT8 Reserved190; -/** Offset 0x042F - Reserved +/** Offset 0x042C - Reserved **/ UINT8 Reserved191; -/** Offset 0x0430 - Reserved +/** Offset 0x042D - Reserved **/ UINT8 Reserved192; -/** Offset 0x0431 - Reserved +/** Offset 0x042E - Reserved **/ UINT8 Reserved193; -/** Offset 0x0432 - Reserved +/** Offset 0x042F - Reserved **/ UINT8 Reserved194; -/** Offset 0x0433 - Reserved -**/ - UINT8 Reserved195; - -/** Offset 0x0434 - GPIO Override - Gpio Override Level - FSP will not configure any GPIOs and rely on GPIO setings - before moved to FSP. Available configurations 0: Disable; 1: Level 1 - Skips GPIO - configuration in PEI/FSPM/FSPT phase;2: Level 2 - Reserved for future use +/** Offset 0x0430 - Reserved **/ - UINT8 GpioOverride; + UINT16 Reserved195[15]; -/** Offset 0x0435 - Reserved +/** Offset 0x044E - Reserved **/ - UINT8 Reserved196[3]; + UINT8 Reserved196[15]; -/** Offset 0x0438 - Reserved +/** Offset 0x045D - Reserved **/ - UINT32 Reserved197; + UINT8 Reserved197[15]; -/** Offset 0x043C - Reserved +/** Offset 0x046C - Reserved **/ - UINT32 Reserved198; + UINT8 Reserved198; -/** Offset 0x0440 - Reserved +/** Offset 0x046D - Reserved **/ UINT8 Reserved199; -/** Offset 0x0441 - Reserved +/** Offset 0x046E - Reserved **/ - UINT8 Reserved200[7]; + UINT8 Reserved200; -/** Offset 0x0448 - Reserved +/** Offset 0x046F - Reserved **/ - UINT64 Reserved201; + UINT8 Reserved201; -/** Offset 0x0450 - Reserved +/** Offset 0x0470 - Reserved **/ UINT8 Reserved202; -/** Offset 0x0451 - Reserved +/** Offset 0x0471 - Reserved **/ UINT8 Reserved203; -/** Offset 0x0452 - Reserved +/** Offset 0x0472 - GPIO Override + Gpio Override Level - FSP will not configure any GPIOs and rely on GPIO setings + before moved to FSP. Available configurations 0: Disable; 1: Level 1 - Skips GPIO + configuration in PEI/FSPM/FSPT phase;2: Level 2 - Reserved for future use +**/ + UINT8 GpioOverride; + +/** Offset 0x0473 - Reserved **/ - UINT16 Reserved204; + UINT8 Reserved204; -/** Offset 0x0454 - Reserved +/** Offset 0x0474 - Reserved **/ - UINT8 Reserved205; + UINT32 Reserved205; -/** Offset 0x0455 - Reserved +/** Offset 0x0478 - Reserved **/ - UINT8 Reserved206; + UINT32 Reserved206; -/** Offset 0x0456 - Reserved +/** Offset 0x047C - Reserved **/ - UINT16 Reserved207; + UINT8 Reserved207; -/** Offset 0x0458 - Reserved +/** Offset 0x047D - Reserved **/ - UINT16 Reserved208[15]; + UINT8 Reserved208[3]; -/** Offset 0x0476 - Reserved +/** Offset 0x0480 - Reserved **/ - UINT8 Reserved209[15]; + UINT64 Reserved209; -/** Offset 0x0485 - Reserved +/** Offset 0x0488 - Reserved **/ - UINT8 Reserved210[15]; + UINT8 Reserved210; -/** Offset 0x0494 - Reserved +/** Offset 0x0489 - Reserved **/ UINT8 Reserved211; -/** Offset 0x0495 - Reserved +/** Offset 0x048A - Reserved **/ - UINT8 Reserved212; + UINT16 Reserved212; -/** Offset 0x0496 - Reserved +/** Offset 0x048C - Reserved **/ UINT8 Reserved213; -/** Offset 0x0497 - Reserved +/** Offset 0x048D - Reserved **/ UINT8 Reserved214; -/** Offset 0x0498 - Reserved +/** Offset 0x048E - Reserved **/ - UINT8 Reserved215; + UINT16 Reserved215; -/** Offset 0x0499 - Reserved +/** Offset 0x0490 - Reserved **/ - UINT8 Reserved216[28]; + UINT16 Reserved216[15]; -/** Offset 0x04B5 - Reserved +/** Offset 0x04AE - Reserved **/ - UINT8 Reserved217; + UINT8 Reserved217[15]; -/** Offset 0x04B6 - Reserved +/** Offset 0x04BD - Reserved **/ - UINT8 Reserved218; + UINT8 Reserved218[15]; -/** Offset 0x04B7 - Reserved +/** Offset 0x04CC - Reserved **/ UINT8 Reserved219; -/** Offset 0x04B8 - Reserved +/** Offset 0x04CD - Reserved **/ - UINT16 Reserved220; + UINT8 Reserved220; -/** Offset 0x04BA - Reserved +/** Offset 0x04CE - Reserved **/ - UINT16 Reserved221[5]; + UINT8 Reserved221; -/** Offset 0x04C4 - Reserved +/** Offset 0x04CF - Reserved **/ - UINT16 Reserved222[5]; + UINT8 Reserved222; -/** Offset 0x04CE - Reserved +/** Offset 0x04D0 - Reserved **/ - UINT16 Reserved223[5]; + UINT8 Reserved223; -/** Offset 0x04D8 - Reserved +/** Offset 0x04D1 - Reserved **/ - UINT16 Reserved224[5]; + UINT8 Reserved224; -/** Offset 0x04E2 - Reserved +/** Offset 0x04D2 - Reserved **/ - UINT16 Reserved225[5]; + UINT8 Reserved225[8]; -/** Offset 0x04EC - Reserved +/** Offset 0x04DA - Reserved **/ - UINT16 Reserved226[5]; + UINT8 Reserved226[8]; -/** Offset 0x04F6 - Reserved +/** Offset 0x04E2 - Reserved **/ - UINT8 Reserved227[5]; + UINT8 Reserved227[29]; -/** Offset 0x04FB - Reserved +/** Offset 0x04FF - Reserved **/ - UINT8 Reserved228[5]; + UINT8 Reserved228; /** Offset 0x0500 - Reserved **/ - UINT16 Reserved229[5]; + UINT8 Reserved229; -/** Offset 0x050A - Reserved +/** Offset 0x0501 - Reserved **/ - UINT16 Reserved230[5]; + UINT8 Reserved230; -/** Offset 0x0514 - Reserved +/** Offset 0x0502 - Reserved **/ - UINT8 Reserved231[5]; + UINT16 Reserved231; -/** Offset 0x0519 - Thermal Design Current enable/disable - PCODE MMIO Mailbox: Thermal Design Current enable/disable; <b>0: Disable</b>; 1: - Enable.For all VR Indexes +/** Offset 0x0504 - Reserved **/ - UINT8 TdcEnable[5]; + UINT16 Reserved232[5]; -/** Offset 0x051E - Reserved +/** Offset 0x050E - Reserved **/ - UINT8 Reserved232[2]; + UINT16 Reserved233[5]; -/** Offset 0x0520 - Thermal Design Current time window - PCODE MMIO Mailbox: Thermal Design Current time window. Defined in milli seconds. - Range 1ms to 448s +/** Offset 0x0518 - Reserved **/ - UINT32 TdcTimeWindow[5]; + UINT16 Reserved234[5]; -/** Offset 0x0534 - Reserved +/** Offset 0x0522 - Reserved **/ - UINT8 Reserved233[5]; + UINT16 Reserved235[5]; -/** Offset 0x0539 - Reserved +/** Offset 0x052C - Reserved **/ - UINT8 Reserved234; + UINT16 Reserved236[5]; -/** Offset 0x053A - Reserved +/** Offset 0x0536 - Reserved **/ - UINT16 Reserved235; + UINT16 Reserved237[5]; -/** Offset 0x053C - Reserved +/** Offset 0x0540 - Reserved **/ - UINT8 Reserved236; + UINT8 Reserved238[5]; -/** Offset 0x053D - Reserved +/** Offset 0x0545 - Reserved **/ - UINT8 Reserved237; + UINT8 Reserved239[5]; -/** Offset 0x053E - Reserved +/** Offset 0x054A - Reserved **/ - UINT8 Reserved238; + UINT16 Reserved240[5]; -/** Offset 0x053F - Reserved +/** Offset 0x0554 - Reserved **/ - UINT8 Reserved239; + UINT16 Reserved241[5]; -/** Offset 0x0540 - Reserved +/** Offset 0x055E - Reserved **/ - UINT8 Reserved240; + UINT8 Reserved242[5]; -/** Offset 0x0541 - Reserved +/** Offset 0x0563 - Thermal Design Current enable/disable + Thermal Design Current enable/disable; <b>0: Disable</b>; 1: Enable. [0] for IA, + [1] for GT, [2] for SA, [3] and [4] are Reserved. **/ - UINT8 Reserved241[1]; + UINT8 TdcEnable[5]; -/** Offset 0x0542 - Reserved +/** Offset 0x0568 - Thermal Design Current time window + TDC Time Window, value of IA either in milliseconds or seconds, value of GT/SA is + in milliseconds. 1ms is default. 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NOTE BIT mask corresponds to - BITS [19:6] Default is 0x30CC -**/ - UINT16 ChHashMask; - -/** Offset 0x09B0 - Reserved +/** Offset 0x09EB - Reserved **/ - UINT32 Reserved426; + UINT8 Reserved426; -/** Offset 0x09B4 - Reserved +/** Offset 0x09EC - Reserved **/ - UINT16 Reserved427; + UINT8 Reserved427; -/** Offset 0x09B6 - Reserved +/** Offset 0x09ED - Reserved **/ - UINT16 Reserved428; + UINT8 Reserved428; -/** Offset 0x09B8 - Reserved +/** Offset 0x09EE - Reserved **/ UINT8 Reserved429; -/** Offset 0x09B9 - Reserved +/** Offset 0x09EF - Reserved **/ UINT8 Reserved430; -/** Offset 0x09BA - Reserved +/** Offset 0x09F0 - Reserved **/ UINT8 Reserved431; -/** Offset 0x09BB - Reserved +/** Offset 0x09F1 - Reserved **/ UINT8 Reserved432; -/** Offset 0x09BC - Reserved +/** Offset 0x09F2 - Reserved **/ UINT8 Reserved433; -/** Offset 0x09BD - Reserved +/** Offset 0x09F3 - Reserved **/ UINT8 Reserved434; -/** Offset 0x09BE - Reserved +/** Offset 0x09F4 - Reserved **/ UINT8 Reserved435; -/** Offset 0x09BF - Reserved +/** Offset 0x09F5 - Reserved **/ UINT8 Reserved436; -/** Offset 0x09C0 - Reserved +/** Offset 0x09F6 - Ch Hash Mask + Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to + BITS [19:6] Default is 0x30CC +**/ + UINT16 ChHashMask; + +/** Offset 0x09F8 - Reserved **/ - UINT8 Reserved437; + UINT32 Reserved437; -/** Offset 0x09C1 - Reserved +/** Offset 0x09FC - Reserved **/ - UINT8 Reserved438; + UINT16 Reserved438; -/** Offset 0x09C2 - Reserved +/** Offset 0x09FE - Reserved **/ - UINT8 Reserved439; + UINT16 Reserved439; -/** Offset 0x09C3 - Reserved +/** Offset 0x0A00 - Reserved **/ UINT8 Reserved440; -/** Offset 0x09C4 - Reserved +/** Offset 0x0A01 - Reserved **/ UINT8 Reserved441; -/** Offset 0x09C5 - Reserved +/** Offset 0x0A02 - Reserved **/ UINT8 Reserved442; -/** Offset 0x09C6 - Reserved +/** Offset 0x0A03 - Reserved **/ UINT8 Reserved443; -/** Offset 0x09C7 - Reserved +/** Offset 0x0A04 - Reserved **/ UINT8 Reserved444; -/** Offset 0x09C8 - Reserved +/** Offset 0x0A05 - Reserved **/ UINT8 Reserved445; -/** Offset 0x09C9 - Reserved +/** Offset 0x0A06 - Reserved **/ UINT8 Reserved446; -/** Offset 0x09CA - Reserved +/** Offset 0x0A07 - Reserved **/ UINT8 Reserved447; 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-/** Offset 0x0A28 - Reserved +/** Offset 0x0A70 - Reserved **/ - UINT8 Reserved513; + UINT8 Reserved524; -/** Offset 0x0A29 - Lock PCU Thermal Management registers +/** Offset 0x0A71 - Lock PCU Thermal Management registers Lock PCU Thermal Management registers. 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+ UINT8 Reserved539; -/** Offset 0x0AA5 - Reserved +/** Offset 0x0AED - Reserved **/ - UINT8 Reserved529; + UINT8 Reserved540; -/** Offset 0x0AA6 - Reserved +/** Offset 0x0AEE - Reserved **/ - UINT8 Reserved530; + UINT8 Reserved541; -/** Offset 0x0AA7 - Reserved +/** Offset 0x0AEF - Reserved **/ - UINT8 Reserved531; + UINT8 Reserved542; -/** Offset 0x0AA8 - Reserved +/** Offset 0x0AF0 - Reserved **/ - UINT8 Reserved532; + UINT8 Reserved543; -/** Offset 0x0AA9 - Reserved +/** Offset 0x0AF1 - Reserved **/ - UINT8 Reserved533; + UINT8 Reserved544; -/** Offset 0x0AAA - Skip CPU replacement check +/** Offset 0x0AF2 - Skip CPU replacement check Test, 0: disable, 1: enable, Setting this option to skip CPU replacement check $EN_DIS **/ UINT8 SkipCpuReplacementCheck; -/** Offset 0x0AAB - Reserved +/** Offset 0x0AF3 - Reserved **/ - UINT8 Reserved534; + UINT8 Reserved545; -/** Offset 0x0AAC - Reserved +/** Offset 0x0AF4 - Reserved **/ - UINT8 Reserved535; + UINT8 Reserved546; -/** Offset 0x0AAD - Serial Io Uart Debug Mode +/** Offset 0x0AF5 - Serial Io Uart Debug Mode Select SerialIo Uart Controller mode 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom, 4:SerialIoUartSkipInit **/ UINT8 SerialIoUartDebugMode; -/** Offset 0x0AAE - Reserved +/** Offset 0x0AF6 - Reserved **/ - UINT8 Reserved536[2]; + UINT8 Reserved547[2]; -/** Offset 0x0AB0 - Reserved +/** Offset 0x0AF8 - Reserved **/ - UINT32 Reserved537; + UINT32 Reserved548; -/** Offset 0x0AB4 - Reserved +/** Offset 0x0AFC - Reserved **/ - UINT32 Reserved538; + UINT32 Reserved549; -/** Offset 0x0AB8 - Reserved +/** Offset 0x0B00 - Reserved **/ - UINT32 Reserved539; + UINT32 Reserved550; -/** Offset 0x0ABC - Reserved +/** Offset 0x0B04 - Reserved **/ - UINT32 Reserved540; + UINT32 Reserved551; -/** Offset 0x0AC0 - Reserved +/** Offset 0x0B08 - Reserved **/ - UINT32 Reserved541; + UINT32 Reserved552; -/** Offset 0x0AC4 - Reserved +/** Offset 0x0B0C - Reserved **/ - UINT8 Reserved542[8]; + UINT8 Reserved553[8]; -/** Offset 0x0ACC - Reserved +/** Offset 0x0B14 - Reserved **/ - UINT8 Reserved543[7]; + UINT8 Reserved554[7]; -/** Offset 0x0AD3 - Reserved +/** Offset 0x0B1B - Reserved **/ - UINT8 Reserved544[5]; + UINT8 Reserved555[5]; } FSP_M_CONFIG; /** Fsp M UPD Configuration @@ -3060,11 +3101,11 @@ typedef struct { **/ FSP_M_CONFIG FspmConfig; -/** Offset 0x0AD8 +/** Offset 0x0B20 **/ - UINT8 UnusedUpdSpace35[6]; + UINT8 UnusedUpdSpace37[6]; -/** Offset 0x0ADE +/** Offset 0x0B26 **/ UINT16 UpdTerminator; } FSPM_UPD; diff --git a/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspsUpd.h index 2fa44f3193da..1460c1fff3b9 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspsUpd.h @@ -2473,164 +2473,180 @@ typedef struct { /** Offset 0x1152 - Reserved **/ - UINT8 Reserved479; + UINT8 Reserved479[6]; -/** Offset 0x1153 - Reserved +/** Offset 0x1158 - Reserved **/ - UINT8 Reserved480; + UINT64 Reserved480; -/** Offset 0x1154 - Reserved +/** Offset 0x1160 - Reserved **/ - UINT16 Reserved481; + UINT64 Reserved481; -/** Offset 0x1156 - Reserved +/** Offset 0x1168 - Reserved **/ - UINT16 Reserved482; + UINT8 Reserved482; -/** Offset 0x1158 - Reserved +/** Offset 0x1169 - Reserved **/ - UINT32 Reserved483; + UINT8 Reserved483; -/** Offset 0x115C - Reserved +/** Offset 0x116A - Reserved **/ UINT16 Reserved484; -/** Offset 0x115E - Reserved +/** Offset 0x116C - Reserved **/ - UINT8 Reserved485[16]; + UINT16 Reserved485; /** Offset 0x116E - Reserved **/ - UINT8 Reserved486; - -/** Offset 0x116F - Enable PS_ON. - PS_ON is a new C10 state from the CPU on desktop SKUs that enables a lower power - target that will be required by the California Energy Commission (CEC). When FALSE, - PS_ON is to be disabled. - $EN_DIS -**/ - UINT8 PsOnEnable; + UINT8 Reserved486[2]; /** Offset 0x1170 - Reserved **/ - UINT8 Reserved487; + UINT32 Reserved487; -/** Offset 0x1171 - Reserved +/** Offset 0x1174 - Reserved **/ - UINT8 Reserved488; + UINT16 Reserved488; -/** Offset 0x1172 - Reserved +/** Offset 0x1176 - Reserved **/ - UINT8 Reserved489; + UINT8 Reserved489[16]; -/** Offset 0x1173 - Reserved +/** Offset 0x1186 - Reserved **/ UINT8 Reserved490; -/** Offset 0x1174 - Reserved +/** Offset 0x1187 - Enable PS_ON. + PS_ON is a new C10 state from the CPU on desktop SKUs that enables a lower power + target that will be required by the California Energy Commission (CEC). When FALSE, + PS_ON is to be disabled. + $EN_DIS +**/ + UINT8 PsOnEnable; + +/** Offset 0x1188 - Reserved **/ UINT8 Reserved491; -/** Offset 0x1175 - Reserved +/** Offset 0x1189 - Reserved **/ UINT8 Reserved492; -/** Offset 0x1176 - Reserved +/** Offset 0x118A - Reserved **/ UINT8 Reserved493; -/** Offset 0x1177 - Reserved +/** Offset 0x118B - Reserved **/ UINT8 Reserved494; -/** Offset 0x1178 - Reserved +/** Offset 0x118C - Reserved **/ UINT8 Reserved495; -/** Offset 0x1179 - Reserved +/** Offset 0x118D - Reserved **/ UINT8 Reserved496; -/** Offset 0x117A - Reserved +/** Offset 0x118E - Reserved **/ UINT8 Reserved497; -/** Offset 0x117B - Reserved +/** Offset 0x118F - Reserved **/ UINT8 Reserved498; -/** Offset 0x117C - Reserved +/** Offset 0x1190 - Reserved **/ - UINT32 Reserved499; + UINT8 Reserved499; -/** Offset 0x1180 - Reserved +/** Offset 0x1191 - Reserved **/ UINT8 Reserved500; -/** Offset 0x1181 - Reserved +/** Offset 0x1192 - Reserved **/ UINT8 Reserved501; -/** Offset 0x1182 - Reserved +/** Offset 0x1193 - Reserved **/ - UINT8 Reserved502[12]; + UINT8 Reserved502; -/** Offset 0x118E - Reserved +/** Offset 0x1194 - Reserved **/ - UINT8 Reserved503[12]; + UINT32 Reserved503; -/** Offset 0x119A - Reserved +/** Offset 0x1198 - Reserved **/ - UINT8 Reserved504[12]; + UINT8 Reserved504; -/** Offset 0x11A6 - Reserved +/** Offset 0x1199 - Reserved **/ - UINT8 Reserved505[10]; + UINT8 Reserved505; -/** Offset 0x11B0 - Reserved +/** Offset 0x119A - Reserved **/ - UINT8 Reserved506[10]; + UINT8 Reserved506[12]; -/** Offset 0x11BA - Reserved +/** Offset 0x11A6 - Reserved **/ - UINT8 Reserved507[10]; + UINT8 Reserved507[12]; -/** Offset 0x11C4 - Reserved +/** Offset 0x11B2 - Reserved **/ - UINT8 Reserved508[10]; + UINT8 Reserved508[12]; -/** Offset 0x11CE - Reserved +/** Offset 0x11BE - Reserved **/ UINT8 Reserved509[10]; -/** Offset 0x11D8 - Reserved +/** Offset 0x11C8 - Reserved **/ UINT8 Reserved510[10]; -/** Offset 0x11E2 - Reserved +/** Offset 0x11D2 - Reserved **/ UINT8 Reserved511[10]; -/** Offset 0x11EC - Reserved +/** Offset 0x11DC - Reserved **/ UINT8 Reserved512[10]; -/** Offset 0x11F6 - Skip PAM regsiter lock +/** Offset 0x11E6 - Reserved +**/ + UINT8 Reserved513[10]; + +/** Offset 0x11F0 - Reserved +**/ + UINT8 Reserved514[10]; + +/** Offset 0x11FA - Reserved +**/ + UINT8 Reserved515[10]; + +/** Offset 0x1204 - Reserved +**/ + UINT8 Reserved516[10]; + +/** Offset 0x120E - Skip PAM regsiter lock Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default): PAM registers will be locked by RC $EN_DIS **/ UINT8 SkipPamLock; -/** Offset 0x11F7 - Reserved +/** Offset 0x120F - Reserved **/ - UINT8 Reserved513; + UINT8 Reserved517; -/** Offset 0x11F8 - Reserved +/** Offset 0x1210 - Reserved **/ - UINT8 Reserved514; + UINT8 Reserved518; -/** Offset 0x11F9 - GT Frequency Limit +/** Offset 0x1211 - GT Frequency Limit 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz, 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD: 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz, @@ -2644,636 +2660,641 @@ typedef struct { **/ UINT8 GtFreqMax; -/** Offset 0x11FA - Reserved -**/ - UINT8 Reserved515; - -/** Offset 0x11FB - Reserved +/** Offset 0x1212 - Reserved **/ - UINT8 Reserved516; + UINT8 Reserved519; -/** Offset 0x11FC - Reserved +/** Offset 0x1213 - Reserved **/ - UINT8 Reserved517; - -/** Offset 0x11FD - Reserved -**/ - UINT8 Reserved518; - -/** Offset 0x11FE - Reserved -**/ - UINT8 Reserved519[2]; - -/** Offset 0x1200 - Reserved -**/ - UINT32 Reserved520; + UINT8 Reserved520; -/** Offset 0x1204 - Reserved +/** Offset 0x1214 - Reserved **/ - UINT32 Reserved521; + UINT8 Reserved521; -/** Offset 0x1208 - Reserved +/** Offset 0x1215 - Reserved **/ UINT8 Reserved522; -/** Offset 0x1209 - Reserved +/** Offset 0x1216 - Reserved **/ - UINT8 Reserved523; + UINT8 Reserved523[2]; -/** Offset 0x120A - Reserved +/** Offset 0x1218 - Reserved **/ - UINT8 Reserved524[2]; + UINT32 Reserved524; -/** Offset 0x120C - Reserved +/** Offset 0x121C - Reserved **/ UINT32 Reserved525; -/** Offset 0x1210 - Reserved +/** Offset 0x1220 - Reserved **/ - UINT32 Reserved526; + UINT8 Reserved526; -/** Offset 0x1214 - Reserved +/** Offset 0x1221 - Reserved **/ - UINT8 Reserved527[32]; + UINT8 Reserved527; -/** Offset 0x1234 - Reserved +/** Offset 0x1222 - Reserved **/ - UINT8 Reserved528; + UINT8 Reserved528[2]; -/** Offset 0x1235 - Reserved +/** Offset 0x1224 - Reserved **/ - UINT8 Reserved529[4]; + UINT32 Reserved529; -/** Offset 0x1239 - Enable or Disable HWP - Enable or Disable HWP(Hardware P states) Support. 0: Disable; <b>1: Enable;</b> - 2-3:Reserved - $EN_DIS +/** Offset 0x1228 - Reserved **/ - UINT8 Hwp; + UINT32 Reserved530; -/** Offset 0x123A - Reserved +/** Offset 0x122C - Reserved **/ - UINT8 Reserved530; + UINT8 Reserved531[32]; -/** Offset 0x123B - Reserved +/** Offset 0x124C - Reserved **/ - UINT8 Reserved531; + UINT8 Reserved532; -/** Offset 0x123C - Reserved +/** Offset 0x124D - Reserved **/ - UINT8 Reserved532; + UINT8 Reserved533[4]; -/** Offset 0x123D - Reserved +/** Offset 0x1251 - Enable or Disable HWP + Enable/Disable Intel(R) Speed Shift Technology support. Enabling will expose the + CPPC v2 interface to allow for hardware controlled P-states. 0: Disable; <b>1: + Enable;</b> + $EN_DIS **/ - UINT8 Reserved533; + UINT8 Hwp; -/** Offset 0x123E - Reserved +/** Offset 0x1252 - Reserved **/ UINT8 Reserved534; -/** Offset 0x123F - Reserved +/** Offset 0x1253 - Reserved **/ UINT8 Reserved535; -/** Offset 0x1240 - Reserved +/** Offset 0x1254 - Reserved **/ UINT8 Reserved536; -/** Offset 0x1241 - TCC Activation Offset - TCC Activation Offset. Offset from factory set TCC activation temperature at which - the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation - Temperature, in volts.For SKL Y SKU, the recommended default for this policy is - <b>10</b>, For all other SKUs the recommended default are <b>0</b> -**/ - UINT8 TccActivationOffset; - -/** Offset 0x1242 - Reserved +/** Offset 0x1255 - Reserved **/ UINT8 Reserved537; -/** Offset 0x1243 - Reserved +/** Offset 0x1256 - Reserved **/ UINT8 Reserved538; -/** Offset 0x1244 - Reserved +/** Offset 0x1257 - Reserved **/ UINT8 Reserved539; -/** Offset 0x1245 - Reserved +/** Offset 0x1258 - Reserved **/ UINT8 Reserved540; -/** Offset 0x1246 - Reserved +/** Offset 0x1259 - TCC Activation Offset + TCC Activation Offset. Offset from factory set TCC activation temperature at which + the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation + Temperature, in volts.For SKL Y SKU, the recommended default for this policy is + <b>10</b>, For all other SKUs the recommended default are <b>0</b> +**/ + UINT8 TccActivationOffset; + +/** Offset 0x125A - Reserved **/ UINT8 Reserved541; -/** Offset 0x1247 - Reserved +/** Offset 0x125B - Reserved **/ UINT8 Reserved542; -/** Offset 0x1248 - Reserved +/** Offset 0x125C - Reserved **/ UINT8 Reserved543; -/** Offset 0x1249 - Reserved +/** Offset 0x125D - Reserved **/ UINT8 Reserved544; -/** Offset 0x124A - Reserved +/** Offset 0x125E - Reserved **/ UINT8 Reserved545; -/** Offset 0x124B - Reserved +/** Offset 0x125F - Reserved **/ UINT8 Reserved546; -/** Offset 0x124C - Reserved +/** Offset 0x1260 - Reserved **/ UINT8 Reserved547; -/** Offset 0x124D - Reserved +/** Offset 0x1261 - Reserved **/ UINT8 Reserved548; -/** Offset 0x124E - Reserved +/** Offset 0x1262 - Reserved **/ UINT8 Reserved549; -/** Offset 0x124F - Reserved +/** Offset 0x1263 - Reserved **/ UINT8 Reserved550; -/** Offset 0x1250 - Reserved +/** Offset 0x1264 - Reserved **/ UINT8 Reserved551; -/** Offset 0x1251 - Reserved +/** Offset 0x1265 - Reserved **/ UINT8 Reserved552; -/** Offset 0x1252 - Reserved +/** Offset 0x1266 - Reserved **/ UINT8 Reserved553; -/** Offset 0x1253 - Reserved +/** Offset 0x1267 - Reserved **/ UINT8 Reserved554; -/** Offset 0x1254 - Reserved +/** Offset 0x1268 - Reserved **/ UINT8 Reserved555; -/** Offset 0x1255 - Reserved +/** Offset 0x1269 - Reserved **/ UINT8 Reserved556; -/** Offset 0x1256 - Reserved +/** Offset 0x126A - Reserved **/ UINT8 Reserved557; -/** Offset 0x1257 - Reserved +/** Offset 0x126B - Reserved **/ UINT8 Reserved558; -/** Offset 0x1258 - Reserved +/** Offset 0x126C - Reserved **/ UINT8 Reserved559; -/** Offset 0x1259 - Reserved +/** Offset 0x126D - Reserved **/ UINT8 Reserved560; -/** Offset 0x125A - Reserved +/** Offset 0x126E - Reserved **/ UINT8 Reserved561; -/** Offset 0x125B - Reserved +/** Offset 0x126F - Reserved **/ UINT8 Reserved562; -/** Offset 0x125C - Enable or Disable Energy Efficient Turbo - Enable or Disable Energy Efficient Turbo, will be applied in Turbo mode. <b>0: Disable</b>; 1: Enable - $EN_DIS -**/ - UINT8 EnergyEfficientTurbo; - -/** Offset 0x125D - Reserved +/** Offset 0x1270 - Reserved **/ UINT8 Reserved563; -/** Offset 0x125E - Reserved +/** Offset 0x1271 - Reserved **/ UINT8 Reserved564; -/** Offset 0x125F - Reserved +/** Offset 0x1272 - Reserved **/ UINT8 Reserved565; -/** Offset 0x1260 - Reserved +/** Offset 0x1273 - Reserved **/ UINT8 Reserved566; -/** Offset 0x1261 - Reserved +/** Offset 0x1274 - Enable or Disable Energy Efficient Turbo + Enable/Disable Energy Efficient Turbo Feature. This feature will opportunistically + lower the turbo frequency to increase efficiency. Recommended only to disable in + overclocking situations where turbo frequency must remain constant. Otherwise, + leave enabled. <b>0: Disable</b>; 1: Enable + $EN_DIS +**/ + UINT8 EnergyEfficientTurbo; + +/** Offset 0x1275 - Reserved **/ UINT8 Reserved567; -/** Offset 0x1262 - Reserved +/** Offset 0x1276 - Reserved **/ UINT8 Reserved568; -/** Offset 0x1263 - Reserved +/** Offset 0x1277 - Reserved **/ UINT8 Reserved569; -/** Offset 0x1264 - Enable or Disable CPU power states (C-states) - Enable or Disable CPU power states (C-states). 0: Disable; <b>1: Enable</b> - $EN_DIS -**/ - UINT8 Cx; - -/** Offset 0x1265 - Reserved +/** Offset 0x1278 - Reserved **/ UINT8 Reserved570; -/** Offset 0x1266 - Reserved +/** Offset 0x1279 - Reserved **/ UINT8 Reserved571; -/** Offset 0x1267 - Reserved +/** Offset 0x127A - Reserved **/ UINT8 Reserved572; -/** Offset 0x1268 - Reserved +/** Offset 0x127B - Reserved **/ UINT8 Reserved573; -/** Offset 0x1269 - Reserved +/** Offset 0x127C - Enable or Disable CPU power states (C-states) + Enable/Disable CPU Power Management. Allows CPU to go to C states when it's not + 100% utilized. 0: Disable; <b>1: Enable</b> + $EN_DIS +**/ + UINT8 Cx; + +/** Offset 0x127D - Reserved **/ UINT8 Reserved574; -/** Offset 0x126A - Reserved +/** Offset 0x127E - Reserved **/ UINT8 Reserved575; -/** Offset 0x126B - Reserved +/** Offset 0x127F - Reserved **/ UINT8 Reserved576; -/** Offset 0x126C - Reserved +/** Offset 0x1280 - Reserved **/ UINT8 Reserved577; -/** Offset 0x126D - Reserved +/** Offset 0x1281 - Reserved **/ UINT8 Reserved578; -/** Offset 0x126E - Reserved +/** Offset 0x1282 - Reserved **/ UINT8 Reserved579; -/** Offset 0x126F - Reserved +/** Offset 0x1283 - Reserved **/ UINT8 Reserved580; -/** Offset 0x1270 - Reserved +/** Offset 0x1284 - Reserved **/ UINT8 Reserved581; -/** Offset 0x1271 - Reserved +/** Offset 0x1285 - Reserved **/ UINT8 Reserved582; -/** Offset 0x1272 - Reserved +/** Offset 0x1286 - Reserved **/ UINT8 Reserved583; -/** Offset 0x1273 - Reserved +/** Offset 0x1287 - Reserved **/ UINT8 Reserved584; -/** Offset 0x1274 - Reserved +/** Offset 0x1288 - Reserved **/ UINT8 Reserved585; -/** Offset 0x1275 - Reserved +/** Offset 0x1289 - Reserved **/ UINT8 Reserved586; -/** Offset 0x1276 - Reserved +/** Offset 0x128A - Reserved **/ UINT8 Reserved587; -/** Offset 0x1277 - Reserved +/** Offset 0x128B - Reserved **/ - UINT8 Reserved588[40]; + UINT8 Reserved588; -/** Offset 0x129F - Reserved +/** Offset 0x128C - Reserved **/ - UINT8 Reserved589[16]; + UINT8 Reserved589; -/** Offset 0x12AF - Reserved +/** Offset 0x128D - Reserved **/ UINT8 Reserved590; -/** Offset 0x12B0 - Reserved +/** Offset 0x128E - Reserved **/ - UINT32 Reserved591; + UINT8 Reserved591; -/** Offset 0x12B4 - Reserved +/** Offset 0x128F - Reserved **/ - UINT32 Reserved592; + UINT8 Reserved592[40]; -/** Offset 0x12B8 - Reserved +/** Offset 0x12B7 - Reserved **/ - UINT32 Reserved593; + UINT8 Reserved593[16]; -/** Offset 0x12BC - Reserved +/** Offset 0x12C7 - Reserved **/ - UINT32 Reserved594; + UINT8 Reserved594; -/** Offset 0x12C0 - Reserved +/** Offset 0x12C8 - Reserved **/ - UINT16 Reserved595; + UINT32 Reserved595; -/** Offset 0x12C2 - Reserved +/** Offset 0x12CC - Reserved **/ - UINT8 Reserved596[2]; + UINT32 Reserved596; -/** Offset 0x12C4 - Reserved +/** Offset 0x12D0 - Reserved **/ UINT32 Reserved597; -/** Offset 0x12C8 - Reserved +/** Offset 0x12D4 - Reserved **/ UINT32 Reserved598; -/** Offset 0x12CC - Reserved +/** Offset 0x12D8 - Reserved **/ - UINT32 Reserved599; + UINT16 Reserved599; -/** Offset 0x12D0 - Reserved +/** Offset 0x12DA - Reserved **/ - UINT32 Reserved600; + UINT8 Reserved600[2]; -/** Offset 0x12D4 - Reserved +/** Offset 0x12DC - Reserved **/ UINT32 Reserved601; -/** Offset 0x12D8 - Reserved +/** Offset 0x12E0 - Reserved **/ UINT32 Reserved602; -/** Offset 0x12DC - Reserved +/** Offset 0x12E4 - Reserved **/ UINT32 Reserved603; -/** Offset 0x12E0 - Reserved +/** Offset 0x12E8 - Reserved **/ UINT32 Reserved604; -/** Offset 0x12E4 - Reserved +/** Offset 0x12EC - Reserved **/ UINT32 Reserved605; -/** Offset 0x12E8 - Reserved +/** Offset 0x12F0 - Reserved **/ - UINT8 Reserved606; + UINT32 Reserved606; -/** Offset 0x12E9 - Reserved +/** Offset 0x12F4 - Reserved **/ - UINT8 Reserved607; + UINT32 Reserved607; -/** Offset 0x12EA - Reserved +/** Offset 0x12F8 - Reserved **/ - UINT8 Reserved608; + UINT32 Reserved608; -/** Offset 0x12EB - Reserved +/** Offset 0x12FC - Reserved **/ - UINT8 Reserved609[4]; + UINT32 Reserved609; -/** Offset 0x12EF - Reserved +/** Offset 0x1300 - Reserved **/ UINT8 Reserved610; -/** Offset 0x12F0 - Reserved +/** Offset 0x1301 - Reserved **/ UINT8 Reserved611; -/** Offset 0x12F1 - Reserved +/** Offset 0x1302 - Reserved **/ UINT8 Reserved612; -/** Offset 0x12F2 - Reserved +/** Offset 0x1303 - Reserved **/ - UINT8 Reserved613; + UINT8 Reserved613[4]; -/** Offset 0x12F3 - Reserved +/** Offset 0x1307 - Reserved **/ UINT8 Reserved614; -/** Offset 0x12F4 - Reserved +/** Offset 0x1308 - Reserved **/ UINT8 Reserved615; -/** Offset 0x12F5 - Reserved +/** Offset 0x1309 - Reserved **/ UINT8 Reserved616; -/** Offset 0x12F6 - Reserved +/** Offset 0x130A - Reserved **/ UINT8 Reserved617; -/** Offset 0x12F7 - Reserved +/** Offset 0x130B - Reserved **/ UINT8 Reserved618; -/** Offset 0x12F8 - Reserved +/** Offset 0x130C - Reserved **/ UINT8 Reserved619; -/** Offset 0x12F9 - Reserved +/** Offset 0x130D - Reserved **/ UINT8 Reserved620; -/** Offset 0x12FA - Reserved +/** Offset 0x130E - Reserved **/ - UINT8 Reserved621[16]; + UINT8 Reserved621; -/** Offset 0x130A - Reserved +/** Offset 0x130F - Reserved **/ - UINT8 Reserved622[16]; + UINT8 Reserved622; -/** Offset 0x131A - End of Post message +/** Offset 0x1310 - Reserved +**/ + UINT8 Reserved623; + +/** Offset 0x1311 - Reserved +**/ + UINT8 Reserved624; + +/** Offset 0x1312 - Reserved +**/ + UINT8 Reserved625[16]; + +/** Offset 0x1322 - Reserved +**/ + UINT8 Reserved626[16]; + +/** Offset 0x1332 - End of Post message Test, Send End of Post message. Disable(0x0): Disable EOP message, Send in PEI(0x1): EOP send in PEI, Send in DXE(0x2)(Default): EOP send in DXE 0:Disable, 1:Send in PEI, 2:Send in DXE, 3:Reserved **/ UINT8 EndOfPostMessage; -/** Offset 0x131B - Reserved +/** Offset 0x1333 - Reserved **/ - UINT8 Reserved623; + UINT8 Reserved627; -/** Offset 0x131C - Reserved +/** Offset 0x1334 - Reserved **/ - UINT8 Reserved624; + UINT8 Reserved628; -/** Offset 0x131D - Reserved +/** Offset 0x1335 - Reserved **/ - UINT8 Reserved625; + UINT8 Reserved629; -/** Offset 0x131E - Reserved +/** Offset 0x1336 - Reserved **/ - UINT8 Reserved626; + UINT8 Reserved630; -/** Offset 0x131F - Reserved +/** Offset 0x1337 - Reserved **/ - UINT8 Reserved627; + UINT8 Reserved631; -/** Offset 0x1320 - Reserved +/** Offset 0x1338 - Reserved **/ - UINT8 Reserved628[16]; + UINT8 Reserved632[16]; -/** Offset 0x1330 - Enable LOCKDOWN SMI +/** Offset 0x1348 - Enable LOCKDOWN SMI Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit. $EN_DIS **/ UINT8 PchLockDownGlobalSmi; -/** Offset 0x1331 - Enable LOCKDOWN BIOS Interface +/** Offset 0x1349 - Enable LOCKDOWN BIOS Interface Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register. $EN_DIS **/ UINT8 PchLockDownBiosInterface; -/** Offset 0x1332 - Unlock all GPIO pads +/** Offset 0x134A - Unlock all GPIO pads Force all GPIO pads to be unlocked for debug purpose. $EN_DIS **/ UINT8 PchUnlockGpioPads; -/** Offset 0x1333 - Reserved +/** Offset 0x134B - Reserved **/ - UINT8 Reserved629; + UINT8 Reserved633; -/** Offset 0x1334 - PCIE RP Ltr Max Snoop Latency +/** Offset 0x134C - PCIE RP Ltr Max Snoop Latency Latency Tolerance Reporting, Max Snoop Latency. **/ UINT16 PcieRpLtrMaxSnoopLatency[24]; -/** Offset 0x1364 - PCIE RP Ltr Max No Snoop Latency +/** Offset 0x137C - PCIE RP Ltr Max No Snoop Latency Latency Tolerance Reporting, Max Non-Snoop Latency. **/ UINT16 PcieRpLtrMaxNoSnoopLatency[24]; -/** Offset 0x1394 - Reserved +/** Offset 0x13AC - Reserved **/ - UINT8 Reserved630[28]; + UINT8 Reserved634[28]; -/** Offset 0x13B0 - Reserved +/** Offset 0x13C8 - Reserved **/ - UINT8 Reserved631[28]; + UINT8 Reserved635[28]; -/** Offset 0x13CC - Reserved +/** Offset 0x13E4 - Reserved **/ - UINT16 Reserved632[24]; + UINT16 Reserved636[24]; -/** Offset 0x13FC - Reserved +/** Offset 0x1414 - Reserved **/ - UINT8 Reserved633[28]; + UINT8 Reserved637[28]; -/** Offset 0x1418 - Reserved +/** Offset 0x1430 - Reserved **/ - UINT8 Reserved634[28]; + UINT8 Reserved638[28]; -/** Offset 0x1434 - Reserved +/** Offset 0x144C - Reserved **/ - UINT16 Reserved635[24]; + UINT16 Reserved639[24]; -/** Offset 0x1464 - Reserved +/** Offset 0x147C - Reserved **/ - UINT8 Reserved636[28]; + UINT8 Reserved640[28]; -/** Offset 0x1480 - Reserved +/** Offset 0x1498 - Reserved **/ - UINT16 Reserved637[24]; + UINT16 Reserved641[24]; -/** Offset 0x14B0 - Reserved +/** Offset 0x14C8 - Reserved **/ - UINT8 Reserved638; + UINT8 Reserved642; -/** Offset 0x14B1 - Reserved +/** Offset 0x14C9 - Reserved **/ - UINT8 Reserved639; + UINT8 Reserved643; -/** Offset 0x14B2 - PCH Energy Reporting +/** Offset 0x14CA - PCH Energy Reporting Disable/Enable PCH to CPU energy report feature. $EN_DIS **/ UINT8 PchPmDisableEnergyReport; -/** Offset 0x14B3 - Reserved +/** Offset 0x14CB - Reserved **/ - UINT8 Reserved640; + UINT8 Reserved644; -/** Offset 0x14B4 - Reserved +/** Offset 0x14CC - Reserved **/ - UINT8 Reserved641; + UINT8 Reserved645; -/** Offset 0x14B5 - Low Power Mode Enable/Disable config mask +/** Offset 0x14CD - Low Power Mode Enable/Disable config mask Configure if respective S0i2/3 sub-states are to be supported. Each bit corresponds to one sub-state (LPMx - BITx): LPM0-s0i2.0, LPM1-s0i2.1, LPM2-s0i2.2, LPM3-s0i3.0, LPM4-s0i3.1, LPM5-s0i3.2, LPM6-s0i3.3, LPM7-s0i3.4. **/ UINT8 PmcLpmS0ixSubStateEnableMask; -/** Offset 0x14B6 - Reserved +/** Offset 0x14CE - Reserved **/ - UINT8 Reserved642; + UINT8 Reserved646; -/** Offset 0x14B7 - Reserved +/** Offset 0x14CF - Reserved **/ - UINT8 Reserved643; + UINT8 Reserved647; -/** Offset 0x14B8 - Reserved +/** Offset 0x14D0 - Reserved **/ - UINT8 Reserved644[8]; + UINT8 Reserved648[8]; -/** Offset 0x14C0 - Reserved +/** Offset 0x14D8 - Reserved **/ - UINT8 Reserved645[8]; + UINT8 Reserved649[8]; -/** Offset 0x14C8 - Reserved +/** Offset 0x14E0 - Reserved **/ - UINT8 Reserved646[8]; + UINT8 Reserved650[8]; -/** Offset 0x14D0 - Reserved +/** Offset 0x14E8 - Reserved **/ - UINT8 Reserved647[8]; + UINT8 Reserved651[8]; -/** Offset 0x14D8 - Reserved +/** Offset 0x14F0 - Reserved **/ - UINT32 Reserved648; + UINT32 Reserved652; -/** Offset 0x14DC - Reserved +/** Offset 0x14F4 - Reserved **/ - UINT8 Reserved649[4]; + UINT8 Reserved653[4]; -/** Offset 0x14E0 - Reserved +/** Offset 0x14F8 - Reserved **/ - UINT8 Reserved650[4]; + UINT8 Reserved654[4]; -/** Offset 0x14E4 - Reserved +/** Offset 0x14FC - Reserved **/ - UINT8 Reserved651[4]; + UINT8 Reserved655[4]; -/** Offset 0x14E8 - Reserved +/** Offset 0x1500 - Reserved **/ - UINT8 Reserved652[5]; + UINT8 Reserved656[5]; -/** Offset 0x14ED - Reserved +/** Offset 0x1505 - Reserved **/ - UINT8 Reserved653[3]; + UINT8 Reserved657[3]; } FSP_S_CONFIG; /** Fsp S UPD Configuration @@ -3292,11 +3313,11 @@ typedef struct { **/ FSP_S_CONFIG FspsConfig; -/** Offset 0x14F0 +/** Offset 0x1508 **/ - UINT8 UnusedUpdSpace40[6]; + UINT8 UnusedUpdSpace42[6]; -/** Offset 0x14F6 +/** Offset 0x150E **/ UINT16 UpdTerminator; } FSPS_UPD; |