vc/mediatek/mt8195: Remove unused code and comments

Remove unused code and comment to align with the latest MTK memory
reference code which is from MTK internal dram driver code without
upstream.
version: Ib59134533ced8de09d23dd9f347c934d315166e2

TEST=boot to kernel

Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com>
Change-Id: I95ab3cf8809ad22a341ceb7fd53a68e13fb0420d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58635
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 114 insertions, 175 deletions

diff --git a/src/vendorcode/mediatek/mt8195/dramc/ANA_init_config.c b/src/vendorcode/mediatek/mt8195/dramc/ANA_init_config.c
index e09f5ea8b4a1..05d0eb903bd1 100644
--- a/src/vendorcode/mediatek/mt8195/dramc/ANA_init_config.c
+++ b/src/vendorcode/mediatek/mt8195/dramc/ANA_init_config.c
@@ -3,19 +3,19 @@
 #include "dramc_dv_init.h"
 #include "dramc_common.h"
 #include "dramc_top.h"
-//==========================
-//PLL config
-//==========================
+
+
+
 static void ANA_PLL_shuffle_Config(DRAMC_CTX_T *p,U32 PLL_FREQ,U16 data_rate)
 {
     U32 XTAL_FREQ = 26;
-    U8  PREDIV    = 1;  //0/1/2
-    U8  POSDIV    = 0;  //0/1/2
-    U8  FBKSEL    = 0;  //over 3800 1 otherwise 0
+    U8  PREDIV    = 1;
+    U8  POSDIV    = 0;
+    U8  FBKSEL    = 0;
     U32 PCW;
     U8 DIV16_CK_SEL    = 0;
 
-#if EMI_LPBK_USE_DDR_800 // For Pe_trus DDR1600, sedalpbk DDR800 thru io
+#if EMI_LPBK_USE_DDR_800
     if(p->frequency==800)
     {
         POSDIV = 1;
@@ -25,7 +25,7 @@ static void ANA_PLL_shuffle_Config(DRAMC_CTX_T *p,U32 PLL_FREQ,U16 data_rate)
 #if (fcFOR_CHIP_ID == fc8195)
     if(A_D->DQ_CA_OPEN == 1)
     {
-        DIV16_CK_SEL = 0; // For open loop mode DDR400 = 1600/div4, confirm with WL Lee
+        DIV16_CK_SEL = 0;
     }
     else
 #endif
@@ -39,7 +39,7 @@ static void ANA_PLL_shuffle_Config(DRAMC_CTX_T *p,U32 PLL_FREQ,U16 data_rate)
     mcSHOW_DBG_MSG6(("=================================== \n"));
 
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_PHYPLL1), P_Fld(0, PHYPLL1_RG_RPHYPLL_TST_EN) | P_Fld(0, PHYPLL1_RG_RPHYPLL_TSTOP_EN));
-    // @Darren, Mp settings sync @WL
+
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_PHYPLL0)     , P_Fld(0      , SHU_PHYPLL0_RG_RPHYPLL_RESERVED           ) \
                                                                   | P_Fld(0      , SHU_PHYPLL0_RG_RPHYPLL_ICHP           ));
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CLRPLL0)     , P_Fld(0      , SHU_CLRPLL0_RG_RCLRPLL_RESERVED           ) \
@@ -52,25 +52,25 @@ static void ANA_PLL_shuffle_Config(DRAMC_CTX_T *p,U32 PLL_FREQ,U16 data_rate)
                                                                   | P_Fld(POSDIV      , SHU_CLRPLL2_RG_RCLRPLL_POSDIV           ));
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_PHYPLL1)     , P_Fld(PCW         , SHU_PHYPLL1_RG_RPHYPLL_SDM_PCW          ) \
                                                                   | P_Fld(1           , SHU_PHYPLL1_RG_RPHYPLL_SDM_PCW_CHG      ) \
-                                                                  | P_Fld(0           , SHU_PHYPLL1_RG_RPHYPLL_SDM_FRA_EN       )); //for DV could set 1 to solve clock jitter issue.
+                                                                  | P_Fld(0           , SHU_PHYPLL1_RG_RPHYPLL_SDM_FRA_EN       ));
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CLRPLL1)     , P_Fld(PCW         , SHU_CLRPLL1_RG_RCLRPLL_SDM_PCW          ) \
                                                                   | P_Fld(1           , SHU_CLRPLL1_RG_RCLRPLL_SDM_PCW_CHG      ) \
-                                                                  | P_Fld(0           , SHU_CLRPLL1_RG_RCLRPLL_SDM_FRA_EN       )); //for DV could set 1 to solve clock jitter issue.
+                                                                  | P_Fld(0           , SHU_CLRPLL1_RG_RCLRPLL_SDM_FRA_EN       ));
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_PLL1)        , P_Fld(1           , SHU_PLL1_RG_RPHYPLLGP_CK_SEL            ) \
-                                                                  | P_Fld(1           , SHU_PLL1_R_SHU_AUTO_PLL_MUX             ));  //notice here. TODO. should create another function to manage the SPM related
+                                                                  | P_Fld(1           , SHU_PLL1_R_SHU_AUTO_PLL_MUX             ));
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_PHYPLL3)     , P_Fld(0           , SHU_PHYPLL3_RG_RPHYPLL_LVROD_EN         ) \
                                                                   | P_Fld(1           , SHU_PHYPLL3_RG_RPHYPLL_RST_DLY          ) \
                                                                   | P_Fld(FBKSEL      , SHU_PHYPLL3_RG_RPHYPLL_FBKSEL           ));
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CLRPLL3)     , P_Fld(0           , SHU_CLRPLL3_RG_RCLRPLL_LVROD_EN         ) \
                                                                   | P_Fld(1           , SHU_CLRPLL3_RG_RCLRPLL_RST_DLY          ) \
                                                                   | P_Fld(FBKSEL      , SHU_CLRPLL3_RG_RCLRPLL_FBKSEL           ));
-    //if(A_D->DQ_CA_OPEN == 1)
+
     {
         vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_MISC_CLK_CTRL0), P_Fld( A_D->DQ_CA_OPEN   , SHU_MISC_CLK_CTRL0_M_CK_OPENLOOP_MODE_SEL   ));
         vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_PHYPLL3) , P_Fld( A_D->DQ_CA_OPEN          , SHU_PHYPLL3_RG_RPHYPLL_MONCK_EN         ) \
-                                                                  | P_Fld( DIV16_CK_SEL          , SHU_PHYPLL3_RG_RPHYPLL_DIV_CK_SEL       )); //@Darren, DDR250 = 4G/div16, confirm with WL Lee
+                                                                  | P_Fld( DIV16_CK_SEL          , SHU_PHYPLL3_RG_RPHYPLL_DIV_CK_SEL       ));
         vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CLRPLL3) , P_Fld( A_D->DQ_CA_OPEN          , SHU_CLRPLL3_RG_RCLRPLL_MONCK_EN         ) \
-                                                                  | P_Fld( DIV16_CK_SEL          , SHU_CLRPLL3_RG_RCLRPLL_DIV_CK_SEL       )); //@Darren, DDR250 = 4G/div16, confirm with WL Lee
+                                                                  | P_Fld( DIV16_CK_SEL          , SHU_CLRPLL3_RG_RCLRPLL_DIV_CK_SEL       ));
     }
 //    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_PLL2)        , P_Fld(1           , SHU_PLL2_RG_RPHYPLL_ADA_MCK8X_EN_SHU    ));
     mcSHOW_DBG_MSG6(("<<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL\n"));
@@ -79,8 +79,8 @@ static void ANA_PLL_shuffle_Config(DRAMC_CTX_T *p,U32 PLL_FREQ,U16 data_rate)
 
 static void ANA_CLK_DIV_config_setting(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr,ANA_top_config_T *a_cfg)
 {
-    U8 TX_ARDQ_SERMODE=0; //DQ_P2S_RATIO
-    U8 TX_ARCA_SERMODE=0; //CA_P2S_RATIO
+    U8 TX_ARDQ_SERMODE=0;
+    U8 TX_ARCA_SERMODE=0;
     U8 ARDLL_SERMODE_B=0;
     U8 ARDLL_SERMODE_C=0;
     BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0;
@@ -99,7 +99,7 @@ static void ANA_CLK_DIV_config_setting(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr,ANA_to
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ6) , P_Fld(  TX_ARDQ_SERMODE    , SHU_B0_DQ6_RG_RX_ARDQ_RANK_SEL_SER_MODE_B0));
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ6) , P_Fld(  TX_ARDQ_SERMODE    , SHU_B1_DQ6_RG_RX_ARDQ_RANK_SEL_SER_MODE_B1));
 
-    //Justin confirm that DES_MODE -> Deserializer mode, while DQ_P2S_RATIO=16 setting 3 others 2. in fact ANA could support some other mode, Here is an propsal option
+
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD11), P_Fld( (tr->DQ_P2S_RATIO == 16 ) ? 3 : 2 , SHU_CA_CMD11_RG_RX_ARCA_DES_MODE_CA));
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ11) , P_Fld( (tr->DQ_P2S_RATIO == 16 ) ? 3 : 2 , SHU_B0_DQ11_RG_RX_ARDQ_DES_MODE_B0));
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ11) , P_Fld( (tr->DQ_P2S_RATIO == 16 ) ? 3 : 2 , SHU_B1_DQ11_RG_RX_ARDQ_DES_MODE_B1));
@@ -116,14 +116,14 @@ static void ANA_CLK_DIV_config_setting(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr,ANA_to
 
     switch (tr->DQ_AAMCK_DIV)
     {
-        case 0 : { ARDLL_SERMODE_B = (isLP4_DSC)?2:0; break; } //for DSC semi-open B1 has to set 2 and B0 don't care
+        case 0 : { ARDLL_SERMODE_B = (isLP4_DSC)?2:0; break; }
         case 2 : { ARDLL_SERMODE_B = 1; break; }
         case 4 : { ARDLL_SERMODE_B = 2; break; }
         case 8:  { ARDLL_SERMODE_B = 3; break; }
         default: mcSHOW_ERR_MSG(("WARN: tr->DQ_AAMCK_DIV= %2d, Because of DQ_SEMI_OPEN, It's don't care.",tr->DQ_AAMCK_DIV));
     }
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DLL1), P_Fld(ARDLL_SERMODE_B             , SHU_B0_DLL1_RG_ARDLL_SER_MODE_B0));
-    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL1), P_Fld(ARDLL_SERMODE_B             , SHU_B1_DLL1_RG_ARDLL_SER_MODE_B1));//TODO:check
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL1), P_Fld(ARDLL_SERMODE_B             , SHU_B1_DLL1_RG_ARDLL_SER_MODE_B1));
 
     switch (tr->CA_ADMCK_DIV)
     {
@@ -136,13 +136,13 @@ static void ANA_CLK_DIV_config_setting(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr,ANA_to
     vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL1),  P_Fld(ARDLL_SERMODE_C           , SHU_CA_DLL1_RG_ARDLL_SER_MODE_CA));
     DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
 
-    //DQ  SEMI-OPEN register control
+
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ6)             , P_Fld(  tr->DQ_SEMI_OPEN , SHU_B0_DQ6_RG_ARPI_SOPEN_EN_B0         ) \
                                                                          | P_Fld(  tr->DQ_CA_OPEN   , SHU_B0_DQ6_RG_ARPI_OPEN_EN_B0          ));
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ6)             , P_Fld(  tr->DQ_SEMI_OPEN , SHU_B1_DQ6_RG_ARPI_SOPEN_EN_B1         ) \
                                                                          | P_Fld(  tr->DQ_CA_OPEN   , SHU_B1_DQ6_RG_ARPI_OPEN_EN_B1          ));
 
-    //CA  SEMI-OPEN register control
+
     if(tr->CA_SEMI_OPEN == 0)
     {
         vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD6)        , P_Fld( 0         , SHU_CA_CMD6_RG_ARPI_SOPEN_EN_CA        ) \
@@ -154,7 +154,7 @@ static void ANA_CLK_DIV_config_setting(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr,ANA_to
     }
     else
     {
-        // @Darren, for DDR800semi
+
         DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
         vIO32WriteFldMulti_All(DDRPHY_REG_SHU_CA_CMD6        , P_Fld( 1         , SHU_CA_CMD6_RG_ARPI_SOPEN_EN_CA        ) \
                                                                          | P_Fld( 1         , SHU_CA_CMD6_RG_ARPI_SOPEN_CKGEN_EN_CA  ) \
@@ -163,17 +163,17 @@ static void ANA_CLK_DIV_config_setting(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr,ANA_to
                                                                          | P_Fld( 1         , SHU_CA_DLL_ARPI3_RG_ARPI_CLK_EN        ));
         if(!isLP4_DSC)
         {
-            //CHA CA as master
+
             vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL_ARPI3), 1, SHU_CA_DLL_ARPI3_RG_ARPI_MCTL_EN_CA    );
-            //CHB CA as slave
+
             vSetPHY2ChannelMapping(p, CHANNEL_B);
             vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL_ARPI3), 0, SHU_CA_DLL_ARPI3_RG_ARPI_MCTL_EN_CA    );
             #if (CHANNEL_NUM>2)
 			    if (channel_num_auxadc > 2) {
 	            	vSetPHY2ChannelMapping(p, CHANNEL_C);
-		            //CHC CA as master
+
         		    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL_ARPI3), 1, SHU_CA_DLL_ARPI3_RG_ARPI_MCTL_EN_CA    );
-            		//CHD CA as slave
+
 		            vSetPHY2ChannelMapping(p, CHANNEL_D);
         		    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL_ARPI3), 0, SHU_CA_DLL_ARPI3_RG_ARPI_MCTL_EN_CA    );
 			    	}
@@ -181,17 +181,17 @@ static void ANA_CLK_DIV_config_setting(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr,ANA_to
         }
         else
         {
-            //CHA CA as master
+
             vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL_ARPI3), 1, SHU_B1_DLL_ARPI3_RG_ARPI_MCTL_EN_B1        );
-            //CHB CA as slave
+
             vSetPHY2ChannelMapping(p, CHANNEL_B);
             vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL_ARPI3), 0, SHU_B1_DLL_ARPI3_RG_ARPI_MCTL_EN_B1        );
             #if (CHANNEL_NUM>2)
 			    if (channel_num_auxadc > 2) {
 		            vSetPHY2ChannelMapping(p, CHANNEL_C);
-        		    //CHC CA as master
+
 		            vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL_ARPI3), 1, SHU_B1_DLL_ARPI3_RG_ARPI_MCTL_EN_B1        );
-		            //CHD CA as slave
+
 		            vSetPHY2ChannelMapping(p, CHANNEL_D);
 		            vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL_ARPI3), 0, SHU_B1_DLL_ARPI3_RG_ARPI_MCTL_EN_B1        );
 			    	}
@@ -201,21 +201,6 @@ static void ANA_CLK_DIV_config_setting(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr,ANA_to
         vSetPHY2ChannelMapping(p, CHANNEL_A);
         DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
 
-//--------TODO ---20190721 WAITING DPHY KaiHsin & Alucary confirm this RG setting.
-//        if(a_cfg->DLL_ASYNC_EN == 1)
-//        {
-//            //CA as all master
-//            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL_ARPI3)   , P_Fld(1, SHU_CA_DLL_ARPI3_RG_ARPI_MCTL_EN_CA    ));
-//        } else {
-//            DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
-//            //CHA CA as master
-//            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL_ARPI3)   , P_Fld(1, SHU_CA_DLL_ARPI3_RG_ARPI_MCTL_EN_CA    ));
-//            //CHB CA as slave
-//            vSetPHY2ChannelMapping(p, CHANNEL_B);
-//            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL_ARPI3)   , P_Fld(0, SHU_CA_DLL_ARPI3_RG_ARPI_MCTL_EN_CA    ));
-//            vSetPHY2ChannelMapping(p, CHANNEL_A);
-//            DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
-//        }
     }
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD6)        , P_Fld( tr->DQ_CA_OPEN    , SHU_CA_CMD6_RG_ARPI_OPEN_EN_CA        ));
 
@@ -236,9 +221,9 @@ static void ANA_CLK_DIV_config_setting(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr,ANA_to
   mcSHOW_DBG_MSG6(("<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration\n"));
 }
 
-//==========================
-//DLL config
-//==========================
+
+
+
 static void ANA_DLL_non_shuffle_config(DRAMC_CTX_T *p,ANA_top_config_T *a_cfg)
 {
   U8 u1PDZone = (p->frequency >= 2133) ? 0x2 : 0x3;
@@ -349,14 +334,14 @@ static void ANA_DLL_shuffle_Config(DRAMC_CTX_T *p, ANA_top_config_T *a_cfg)
     BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0;
     if(p->frequency<=1600)
     {
-        u1Gain = 1;//checked by WL
+        u1Gain = 1;
 
         mcSHOW_DBG_MSG6((">>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = %d\n",u1Gain));
     }
 
     mcSHOW_DBG_MSG6((">>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL\n"));
 
-    //B0
+
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DLL0)        , P_Fld(  7+u1Gain                       , SHU_B0_DLL0_RG_ARDLL_GAIN_B0         ) \
                                                                      | P_Fld(  7                       , SHU_B0_DLL0_RG_ARDLL_IDLECNT_B0      ) \
                                                                      | P_Fld(  0                       , SHU_B0_DLL0_RG_ARDLL_FAST_PSJP_B0    ) \
@@ -372,7 +357,7 @@ static void ANA_DLL_shuffle_Config(DRAMC_CTX_T *p, ANA_top_config_T *a_cfg)
                                                                      | P_Fld(  0                       , SHU_B0_DLL1_RG_ARDLL_PD_CK_SEL_B0    ));
 if (isLP4_DSC)
 {
-    //B1
+
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL0)        , P_Fld(  7+u1Gain                       , SHU_CA_DLL0_RG_ARDLL_GAIN_CA         ) \
                                                                      | P_Fld(  7                       , SHU_CA_DLL0_RG_ARDLL_IDLECNT_CA      ) \
                                                                      | P_Fld(  0                       , SHU_CA_DLL0_RG_ARDLL_FAST_PSJP_CA    ) \
@@ -481,7 +466,7 @@ if (isLP4_DSC)
 }
 else
 {
-    //B1
+
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL0)        , P_Fld(  7+u1Gain                       , SHU_B1_DLL0_RG_ARDLL_GAIN_B1         ) \
                                                                      | P_Fld(  7                       , SHU_B1_DLL0_RG_ARDLL_IDLECNT_B1      ) \
                                                                      | P_Fld(  0                       , SHU_B1_DLL0_RG_ARDLL_FAST_PSJP_B1    ) \
@@ -595,7 +580,7 @@ else
 static void ANA_ARPI_shuffle_config(DRAMC_CTX_T *p,ANA_top_config_T *a_cfg,ANA_DVFS_CORE_T *tr)
 {
     BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0;
-    //B0
+
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DLL_ARPI3)   , P_Fld(  !((tr->DQ_SEMI_OPEN)||(tr->DQ_CA_OPEN)), SHU_B0_DLL_ARPI3_RG_ARPI_DQSIEN_EN_B0  ) \
                                                                      | P_Fld(  !((tr->DQ_SEMI_OPEN)||(tr->DQ_CA_OPEN)), SHU_B0_DLL_ARPI3_RG_ARPI_DQ_EN_B0      ) \
                                                                      | P_Fld(  !((tr->DQ_SEMI_OPEN)||(tr->DQ_CA_OPEN)), SHU_B0_DLL_ARPI3_RG_ARPI_DQM_EN_B0     ) \
@@ -612,7 +597,7 @@ static void ANA_ARPI_shuffle_config(DRAMC_CTX_T *p,ANA_top_config_T *a_cfg,ANA_D
                                                                      | P_Fld(  0          , SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0   ) \
                                                                      | P_Fld(  0          , SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0   ));
 
-    //B1
+
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL_ARPI3)   , P_Fld(  !((tr->DQ_SEMI_OPEN)||(tr->DQ_CA_OPEN)), SHU_B1_DLL_ARPI3_RG_ARPI_DQSIEN_EN_B1  ) \
                                                                      | P_Fld(  !((tr->DQ_SEMI_OPEN)||(tr->DQ_CA_OPEN)), SHU_B1_DLL_ARPI3_RG_ARPI_DQ_EN_B1      ) \
                                                                      | P_Fld(  !((tr->DQ_SEMI_OPEN)||(tr->DQ_CA_OPEN)), SHU_B1_DLL_ARPI3_RG_ARPI_DQM_EN_B1     ) \
@@ -630,7 +615,7 @@ static void ANA_ARPI_shuffle_config(DRAMC_CTX_T *p,ANA_top_config_T *a_cfg,ANA_D
                                                                      | P_Fld(  0          , SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1   ));
 
 
-    //CA
+
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL_ARPI3)   , P_Fld(  isLP4_DSC&&(!((tr->DQ_SEMI_OPEN)||(tr->DQ_CA_OPEN))), SHU_CA_DLL_ARPI3_RG_ARPI_CLKIEN_EN     ) \
                                                                      | P_Fld(  (!((tr->DQ_SEMI_OPEN)||(tr->DQ_CA_OPEN))), SHU_CA_DLL_ARPI3_RG_ARPI_CMD_EN        ) \
                                                                      | P_Fld(  (!((tr->DQ_SEMI_OPEN)||(tr->DQ_CA_OPEN))), SHU_CA_DLL_ARPI3_RG_ARPI_CS_EN         ));
@@ -644,9 +629,9 @@ static void ANA_ARPI_shuffle_config(DRAMC_CTX_T *p,ANA_top_config_T *a_cfg,ANA_D
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD7)        , P_Fld(  0          , SHU_CA_CMD7_R_DMTX_ARPI_CG_CS_NEW      ) \
                                                                      | P_Fld(  0          , SHU_CA_CMD7_R_DMTX_ARPI_CG_CMD_NEW     ));
 }
-//==========================
-//ANA_TX_CONFIG
-//==========================
+
+
+
 static void ANA_TX_nonshuffle_config(DRAMC_CTX_T *p,ANA_top_config_T *a_cfg)
 {
     BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0;
@@ -660,7 +645,7 @@ static void ANA_TX_nonshuffle_config(DRAMC_CTX_T *p,ANA_top_config_T *a_cfg)
                                                                 | P_Fld(!(a_cfg->LP45_APHY_COMB_EN)  , B1_DQ6_RG_TX_ARDQ_DDR4_SEL_B1        ) \
                                                                 | P_Fld(a_cfg->LP45_APHY_COMB_EN     , B1_DQ6_RG_TX_ARDQ_LP4_SEL_B1         ));
     mcSHOW_DBG_MSG6(("<<<<<< [CONFIGURE PHASE]: ANA_TX\n"));
-    //enable TX OE
+
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ2)        , P_Fld(0                      , B0_DQ2_RG_TX_ARDQ_OE_DIS_B0          ) \
                                                                 | P_Fld(0                      , B0_DQ2_RG_TX_ARDQ_ODTEN_DIS_B0       ) \
                                                                 | P_Fld(0                      , B0_DQ2_RG_TX_ARDQM0_OE_DIS_B0        ) \
@@ -714,13 +699,13 @@ static void ANA_TX_nonshuffle_config(DRAMC_CTX_T *p,ANA_top_config_T *a_cfg)
 
         vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_TX_ARCS_CTRL),P_Fld(1, CA_TX_ARCS_CTRL_RG_TX_ARCS_OE_TIE_SEL_C0)) ;
         vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_TX_ARDQ_CTRL), P_Fld(1, CA_TX_ARDQ_CTRL_RG_TX_ARDQ6_OE_TIE_EN_C0) \
-                                                       | P_Fld(1, CA_TX_ARDQ_CTRL_RG_TX_ARDQ7_OE_TIE_EN_C0)) ; //Sync MP setting WL C0 DQ6 and DQ7 is no use
+                                                       | P_Fld(1, CA_TX_ARDQ_CTRL_RG_TX_ARDQ7_OE_TIE_EN_C0)) ;
         vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_TX_CKE_CTRL), P_Fld(1, B1_TX_CKE_CTRL_RG_TX_ARCKE_OE_TIE_EN_B1) \
-                                                       | P_Fld(1, B1_TX_CKE_CTRL_RG_TX_ARCS1_OE_TIE_EN_B1)) ; //Sync MP setting WL EMCP: B1 CS1 and CKE is no use
+                                                       | P_Fld(1, B1_TX_CKE_CTRL_RG_TX_ARCS1_OE_TIE_EN_B1)) ;
     }
 
 
-    //enable TX & reset
+
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD3)       , P_Fld(1                      , CA_CMD3_RG_TX_ARCMD_EN               ) \
                                                                 | P_Fld(1                      , CA_CMD3_RG_ARCMD_RESETB              ));
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ3)        , P_Fld(1                      , B0_DQ3_RG_ARDQ_RESETB_B0             ) \
@@ -733,7 +718,7 @@ static void ANA_TX_shuffle_config(DRAMC_CTX_T *p,ANA_top_config_T *a_cfg,U8 grou
 {
     BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0;
 
-    //ODTEN & DQS control
+
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD13)  , P_Fld(isLP4_DSC                      , SHU_CA_CMD13_RG_TX_ARCLK_OE_ODTEN_CG_EN_CA        ) \
                                                                 | P_Fld(isLP4_DSC                      , SHU_CA_CMD13_RG_TX_ARCS_OE_ODTEN_CG_EN_CA         )
                                                                 | P_Fld(0           , SHU_CA_CMD13_RG_TX_ARCLK_READ_BASE_EN_CA           )
@@ -767,28 +752,28 @@ static void ANA_TX_shuffle_config(DRAMC_CTX_T *p,ANA_top_config_T *a_cfg,U8 grou
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ14)   , P_Fld(  0                    , SHU_B1_DQ14_RG_TX_ARDQ_MCKIO_SEL_B1               ) \
                                                                 | P_Fld(  0                    , SHU_B1_DQ14_RG_TX_ARWCK_MCKIO_SEL_B1              ));
 
-    //B0
+
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ13), P_Fld(a_cfg->NEW_RANK_MODE, SHU_B0_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B0));
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ2), P_Fld(a_cfg->NEW_RANK_MODE, SHU_B0_DQ2_RG_ARPI_OFFSET_LAT_EN_B0) \
                                                             | P_Fld(a_cfg->NEW_RANK_MODE, SHU_B0_DQ2_RG_ARPI_OFFSET_ASYNC_EN_B0));
     if(!isLP4_DSC)
     {
-    //B1
+
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ13), P_Fld(a_cfg->NEW_RANK_MODE, SHU_B1_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B1));
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ2), P_Fld(a_cfg->NEW_RANK_MODE, SHU_B1_DQ2_RG_ARPI_OFFSET_LAT_EN_B1) \
                                                             | P_Fld(a_cfg->NEW_RANK_MODE, SHU_B1_DQ2_RG_ARPI_OFFSET_ASYNC_EN_B1));
-    //CA
+
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD13), P_Fld(0, SHU_CA_CMD13_RG_TX_ARCA_DLY_LAT_EN_CA));
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD2), P_Fld(0, SHU_CA_CMD2_RG_ARPI_OFFSET_LAT_EN_CA) \
                                                              | P_Fld(0, SHU_CA_CMD2_RG_ARPI_OFFSET_ASYNC_EN_CA));
     }
     else
     {
-    //B1
+
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ13), P_Fld(0, SHU_B1_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B1));
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ2), P_Fld(0, SHU_B1_DQ2_RG_ARPI_OFFSET_LAT_EN_B1) \
                                                             | P_Fld(0, SHU_B1_DQ2_RG_ARPI_OFFSET_ASYNC_EN_B1));
-    //CA
+
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD13), P_Fld(a_cfg->NEW_RANK_MODE, SHU_CA_CMD13_RG_TX_ARCA_DLY_LAT_EN_CA));
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD2), P_Fld(a_cfg->NEW_RANK_MODE, SHU_CA_CMD2_RG_ARPI_OFFSET_LAT_EN_CA) \
                                                              | P_Fld(a_cfg->NEW_RANK_MODE, SHU_CA_CMD2_RG_ARPI_OFFSET_ASYNC_EN_CA));
@@ -796,7 +781,7 @@ static void ANA_TX_shuffle_config(DRAMC_CTX_T *p,ANA_top_config_T *a_cfg,U8 grou
 
 
 #if SA_CONFIG_EN
-    // enable after runtime configs
+
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ13)   , P_Fld( 0, SHU_B0_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B0              ));
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ2)   , P_Fld( 0  , SHU_B0_DQ2_RG_ARPI_OFFSET_LAT_EN_B0              ));
     if(!isLP4_DSC)
@@ -823,12 +808,12 @@ static void ANA_RX_shuffle_config(DRAMC_CTX_T *p,U8 group_id)
 #if (ENABLE_LP4Y_DFS && LP4Y_BACKUP_SOLUTION)
     RDQS_SE_EN        = DFS(group_id)->data_rate<=1600 ? 1 : 0;
 #else
-    RDQS_SE_EN        = 0; //TODO for LPDDR5
+    RDQS_SE_EN        = 0;
 #endif
     DQSIEN_MODE       = DFS(group_id)->DQSIEN_MODE;
     NEW_RANK_MODE     = A_T->NEW_RANK_MODE;
 
-    //B0
+
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ10)   , P_Fld(  RDQS_SE_EN           , SHU_B0_DQ10_RG_RX_ARDQS_SE_EN_B0                 ) \
                                                                 | P_Fld(DQSIEN_MODE            , SHU_B0_DQ10_RG_RX_ARDQS_DQSIEN_MODE_B0           ) \
                                                                 | P_Fld(1                      , SHU_B0_DQ10_RG_RX_ARDQS_DLY_LAT_EN_B0            ) \
@@ -838,7 +823,7 @@ static void ANA_RX_shuffle_config(DRAMC_CTX_T *p,U8 group_id)
                                                                 | P_Fld(NEW_RANK_MODE          , SHU_B0_DQ11_RG_RX_ARDQ_RANK_SEL_LAT_EN_B0        ) );
 
     if(isLP4_DSC){
-    //CA
+
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD10)   , P_Fld(  RDQS_SE_EN           , SHU_CA_CMD10_RG_RX_ARCLK_SE_EN_CA                 ) \
                                                                 | P_Fld(DQSIEN_MODE            , SHU_CA_CMD10_RG_RX_ARCLK_DQSIEN_MODE_CA           ) \
                                                                 | P_Fld(1                      , SHU_CA_CMD10_RG_RX_ARCLK_DLY_LAT_EN_CA            ) \
@@ -849,7 +834,7 @@ static void ANA_RX_shuffle_config(DRAMC_CTX_T *p,U8 group_id)
     }
     else
     {
-    //B1
+
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ10)   , P_Fld(  RDQS_SE_EN           , SHU_B1_DQ10_RG_RX_ARDQS_SE_EN_B1                 ) \
                                                                 | P_Fld(DQSIEN_MODE            , SHU_B1_DQ10_RG_RX_ARDQS_DQSIEN_MODE_B1           ) \
                                                                 | P_Fld(1                      , SHU_B1_DQ10_RG_RX_ARDQS_DLY_LAT_EN_B1            ) \
@@ -859,7 +844,7 @@ static void ANA_RX_shuffle_config(DRAMC_CTX_T *p,U8 group_id)
                                                                 | P_Fld(NEW_RANK_MODE          , SHU_B1_DQ11_RG_RX_ARDQ_RANK_SEL_LAT_EN_B1        ));
     }
     #if SA_CONFIG_EN
-    // enable after runtime configs
+
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ10)   , P_Fld( 0  , SHU_B0_DQ10_RG_RX_ARDQS_DLY_LAT_EN_B0              ));
 
     if(isLP4_DSC){
@@ -885,7 +870,7 @@ static void ANA_RX_nonshuffle_config(DRAMC_CTX_T *p)
 {
     BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0;
 
-    //B0
+
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ5)        , P_Fld( 1                     , B0_DQ5_RG_RX_ARDQ_VREF_EN_B0                     ));
 
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6)        , P_Fld( 0                     , B0_DQ6_RG_RX_ARDQ_DDR3_SEL_B0                    ) \
@@ -898,7 +883,7 @@ static void ANA_RX_nonshuffle_config(DRAMC_CTX_T *p)
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ3)        , P_Fld( 1                     , B0_DQ3_RG_RX_ARDQ_STBENCMP_EN_B0                 ) \
                                                                 | P_Fld( 1                     , B0_DQ3_RG_RX_ARDQ_SMT_EN_B0                      ));
 
-    //B1
+
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ5)        , P_Fld( (!isLP4_DSC)                     , B1_DQ5_RG_RX_ARDQ_VREF_EN_B1                     ));
 
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ6)        , P_Fld( 0                     , B1_DQ6_RG_RX_ARDQ_DDR3_SEL_B1                    ) \
@@ -911,7 +896,7 @@ static void ANA_RX_nonshuffle_config(DRAMC_CTX_T *p)
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ3)        , P_Fld( (!isLP4_DSC)                     , B1_DQ3_RG_RX_ARDQ_STBENCMP_EN_B1                 ) \
                                                                 | P_Fld( (!isLP4_DSC)                     , B1_DQ3_RG_RX_ARDQ_SMT_EN_B1                      ));
 
-    //CA
+
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD5), P_Fld(isLP4_DSC, CA_CMD5_RG_RX_ARCMD_VREF_EN));
 
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD6)       , P_Fld( 0                     , CA_CMD6_RG_RX_ARCMD_DDR3_SEL                     ) \
@@ -924,7 +909,7 @@ static void ANA_RX_nonshuffle_config(DRAMC_CTX_T *p)
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD3), P_Fld(isLP4_DSC, CA_CMD3_RG_RX_ARCMD_STBENCMP_EN) \
                                                          | P_Fld(isLP4_DSC, CA_CMD3_RG_RX_ARCMD_SMT_EN));
 
-    //RX reset
+
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD9)       , P_Fld( 1                     , CA_CMD9_RG_RX_ARCMD_STBEN_RESETB                 ) \
                                                                 | P_Fld( 1                     , CA_CMD9_RG_RX_ARCLK_STBEN_RESETB                 ));
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ9)        , P_Fld( 1                     , B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0                ) \
@@ -932,16 +917,16 @@ static void ANA_RX_nonshuffle_config(DRAMC_CTX_T *p)
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ9)        , P_Fld( 1                     , B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1                ) \
                                                                 | P_Fld( 1                     , B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1              ));
 
-    //Justin confirm that: All set 1  for improving internal timing option
+
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD8)       , P_Fld( 1                     , CA_CMD8_RG_RX_ARCLK_SER_RST_MODE                 ));
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ8)        , P_Fld( 1                     , B0_DQ8_RG_RX_ARDQS_SER_RST_MODE_B0               ));
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ8)        , P_Fld( 1                     , B1_DQ8_RG_RX_ARDQS_SER_RST_MODE_B1               ));
 
 }
 
-//============================================
-// RESET
-//============================================
+
+
+
 void RESETB_PULL_DN(DRAMC_CTX_T *p)
 {
     mcSHOW_DBG_MSG6(("============ PULL DRAM RESETB DOWN ============\n"));
@@ -957,9 +942,9 @@ void RESETB_PULL_DN(DRAMC_CTX_T *p)
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD11)      , P_Fld( 0                     , CA_CMD11_RG_TX_RRESETB_PULL_DN   ));
     mcSHOW_DBG_MSG6(("========== PULL DRAM RESETB DOWN end =========\n"));
 }
-//============================================
-// SUSPEND_OFF_control
-//============================================
+
+
+
 static void SUSPEND_ON(DRAMC_CTX_T *p)
 {
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_LP_CTRL0)   , P_Fld( 0                     , B0_LP_CTRL0_RG_ARDMSUS_10_B0     ));
@@ -968,9 +953,9 @@ static void SUSPEND_ON(DRAMC_CTX_T *p)
     vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_CA_LP_CTRL0)   , P_Fld( 0                     , CA_LP_CTRL0_RG_ARDMSUS_10_CA     ));
     DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
 }
-//============================================
-// SPM_control
-//============================================
+
+
+
 static void SPM_control(DRAMC_CTX_T *p,ANA_top_config_T *a_cfg)
 {
     BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0;
@@ -1069,10 +1054,10 @@ static void SPM_control(DRAMC_CTX_T *p,ANA_top_config_T *a_cfg)
                                                               | P_Fld( 1                  , CA_LP_CTRL0_RG_ARPI_DDR400_EN_CA_LP_SEL) \
                                                               | P_Fld( 1                  , CA_LP_CTRL0_RG_CA_DLL_EN_OP_SEQ_LP_SEL) \
                                                               | P_Fld( 1                  , CA_LP_CTRL0_RG_DA_PICG_CA_CTRL_LOW_BY_LPC) \
-                                                              | P_Fld( 0 , CA_LP_CTRL0_RG_RX_ARCMD_BIAS_EN_LP_SEL       )); //use CA as DQ set 1
+                                                              | P_Fld( 0 , CA_LP_CTRL0_RG_RX_ARCMD_BIAS_EN_LP_SEL       ));
         DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
 
-    REG_TRANSFER_T MS_SLV_LP_SEL_Reg;//TODO:check
+    REG_TRANSFER_T MS_SLV_LP_SEL_Reg;
     if (isLP4_DSC){
         MS_SLV_LP_SEL_Reg.u4Addr = DDRPHY_REG_B1_LP_CTRL0;
         MS_SLV_LP_SEL_Reg.u4Fld = B1_LP_CTRL0_RG_B1_MS_SLV_LP_SEL;
@@ -1106,7 +1091,7 @@ static void SPM_control(DRAMC_CTX_T *p,ANA_top_config_T *a_cfg)
         DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
     }
 
-    //FOR DDR400 OPEN-LOOP MODE
+
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL9), P_Fld( 1           , MISC_CG_CTRL9_RG_M_CK_OPENLOOP_MODE_EN      ) \
                                                                | P_Fld( 1           , MISC_CG_CTRL9_RG_MCK4X_I_OPENLOOP_MODE_EN   ) \
                                                                | P_Fld( 1           , MISC_CG_CTRL9_RG_CG_DDR400_MCK4X_I_OFF      ) \
@@ -1116,7 +1101,7 @@ static void SPM_control(DRAMC_CTX_T *p,ANA_top_config_T *a_cfg)
                                                                | P_Fld( 1           , MISC_CG_CTRL9_RG_CG_DDR400_MCK4X_Q_OFF      ) \
                                                                | P_Fld( 0           , MISC_CG_CTRL9_RG_DDR400_MCK4X_Q_FORCE_ON    ) \
                                                                | P_Fld( 1           , MISC_CG_CTRL9_RG_MCK4X_Q_FB_CK_CG_OFF       ));
-#if 0 // @Darren-, new APHY remove 45/135 phases
+#if 0
                                                                | P_Fld( 1           , MISC_CG_CTRL9_RG_MCK4X_O_OPENLOOP_MODE_EN   ) \
                                                                | P_Fld( 1           , MISC_CG_CTRL9_RG_CG_DDR400_MCK4X_O_OFF      ) \
                                                                | P_Fld( 0           , MISC_CG_CTRL9_RG_DDR400_MCK4X_O_FORCE_ON    ) \
@@ -1126,31 +1111,13 @@ static void SPM_control(DRAMC_CTX_T *p,ANA_top_config_T *a_cfg)
 
 static void DIG_DCM_nonshuffle_config(DRAMC_CTX_T *p)
 {
-    //RX DCM
+
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RX_CG_CTRL), P_Fld(3      , MISC_SHU_RX_CG_CTRL_RX_DCM_EXT_DLY          ));
 }
 
 static void DIG_PHY_SHU_MISC_CG_CTRL(DRAMC_CTX_T *p)
 {
-     //bit 0       : DPHY_NAO_GLUE_B0.mck_dq_cg_ctrl
-     //bit 1       : DPHY_NAO_GLUE_B1.mck_dq_cg_ctrl
-     //bit 2       : DPHY_NAO_GLUE_CA.mck_ca_cg_ctrl
-     //bit 4       : DPHY_NAO_GLUE_B0.rx_mck_dq_cg_ctrl
-     //bit 5       : DPHY_NAO_GLUE_B1.rx_mck_dq_cg_ctrl
-     //bit 6       : DPHY_NAO_GLUE_CA.rx_mck_ca_cg_ctrl
-     //bit [9 : 8] : DPHY_TX_BRIDGE_GLUE.ddrphy_idle
-     //bit [11:10] : DPHY_TX_BRIDGE_GLUE.ddrphy_idle_dq
-     //bit [13:12] : DPHY_TX_BRIDGE_GLUE.ddrphy_idle_tx_cmd
-     //bit [17:16] : DPHY_TX_BRIDGE_GLUE.ddrphy_idle_tx_b0
-     //bit [19:18] : DPHY_TX_BRIDGE_GLUE.ddrphy_idle_tx_b1
-     //bit [22:20] : DPHY_TX_BRIDGE_GLUE.ddrphy_idle_rx_cmd
-     //bit [26:24] : DPHY_TX_BRIDGE_GLUE.ddrphy_idle_rx_b0
-     //bit [30:28] : DPHY_TX_BRIDGE_GLUE.ddrphy_idle_rx_b1
-
-//     vIO32Write4B      (DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_CG_CTRL0), 0x333f3f00);
-//     //1. ignore NAO_GLUE cg ctrl,
-//     2.00:ddrphy_idle/_ca/b0/b1 01: ddrphy_idle_shuopt 10: ddrphy_idle_shuopt_pinmux
-     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_CG_CTRL0), 0x33400000);//rx_cmd_idle tie 1 others DCM control depend on CA B0 B1 independtly -- could save more power
+     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_CG_CTRL0), 0x33400000);
 }
 
 static void ANA_IMP_configure(DRAMC_CTX_T *p)
@@ -1167,18 +1134,14 @@ static void ANA_IMP_configure(DRAMC_CTX_T *p)
 
 static void ANA_CLOCK_SWITCH(DRAMC_CTX_T *p)
 {
-    //OPENLOOP MODE. w_chg_mem_mck1x
+
     if(A_D->DQ_CA_OPEN)
     {
         vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL0)      , P_Fld(  1                , MISC_CG_CTRL0_RESERVED_MISC_CG_CTRL0_BIT3_1));
         mcDELAY_XNS(100);
         vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL0)      , P_Fld(  0                , MISC_CG_CTRL0_RESERVED_MISC_CG_CTRL0_BIT3_1));
     }
-    //mem_sel     _____|------------------------------------
-    //w_chg_mem   ______________|------------|______________
-    //BLCK        __|---|___|---|____________|-|_|-|_|-|_|-
-    //            |<-    26M  ->|<-  MUTE  ->|<-   MCK4X  ->|
-    //before DLL enable switch feedback clock
+
     DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
     vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CKMUX_SEL)     , P_Fld(  1                         , MISC_CKMUX_SEL_R_PHYCTRLDCM          ) \
                                                                      | P_Fld(  1                         , MISC_CKMUX_SEL_R_PHYCTRLMUX          ));
@@ -1186,12 +1149,11 @@ static void ANA_CLOCK_SWITCH(DRAMC_CTX_T *p)
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL0)      , P_Fld(  1                         , MISC_CG_CTRL0_CLK_MEM_SEL            ) \
                                                                      | P_Fld(  1                         , MISC_CG_CTRL0_W_CHG_MEM              ));
 
-    mcDELAY_XNS(100);//reserve 100ns period for clock mute and latch the rising edge sync condition for BCLK
+    mcDELAY_XNS(100);
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL0)      , P_Fld(  0                         , MISC_CG_CTRL0_W_CHG_MEM              ));
 
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL0)      , P_Fld(  1                         , MISC_CG_CTRL0_RG_FREERUN_MCK_CG      ));
 
-    //after clock change, if OPEN LOOP MODE should change clock to 1x.  bit7 is RG_dvfs_clk_mem_mck1x_sel
     if(A_D->DQ_CA_OPEN)
     {
         vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL0)      , P_Fld(  1                , MISC_CG_CTRL0_RESERVED_MISC_CG_CTRL0_BIT7));
@@ -1221,15 +1183,10 @@ void ANA_Config_shuffle(DRAMC_CTX_T *p,ANA_top_config_T *a_cfg,U8 group_id)
     DIG_PHY_SHU_MISC_CG_CTRL(p);
     ANA_CLK_DIV_config_setting(p,A_D,a_cfg);
     ANA_DLL_shuffle_Config(p,a_cfg);
-//    ANA_sequence_shuffle_colletion(p,&ana_core_p);
 }
 
 static void ANA_PHY_Config(DRAMC_CTX_T *p,ANA_top_config_T *a_cfg)
 {
-    //RESET DPM
-    //vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_MD32_REG_SSPM_CFGREG_SW_RSTN), 32'h1000_0001 );
-
-//    SC_DPY_MODE_SW(PULL_UP);
     ANA_Config_nonshuffle(p,a_cfg);
     ANA_Config_shuffle(p,a_cfg,0);
 }
@@ -1253,8 +1210,6 @@ static void ANA_MIDPI_sequence(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr)
     vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ1)   , 1, SHU_B1_DQ1_RG_ARPI_MIDPI_LDO_VREF_SEL_B1   );
     vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD1)  , 1, SHU_CA_CMD1_RG_ARPI_MIDPI_LDO_VREF_SEL_CA   );
 
-    //ASVA 2-6
-    //step1: CG high. --disable 8 phase clk output
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DLL_ARPI2)   , P_Fld(  1         , SHU_B0_DLL_ARPI2_RG_ARPI_MPDIV_CG_B0   ) \
                                                                      | P_Fld(  1         , SHU_B0_DLL_ARPI2_RG_ARPI_CG_FB_B0      ));
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL_ARPI2)   , P_Fld(  1         , SHU_B1_DLL_ARPI2_RG_ARPI_MPDIV_CG_B1   ) \
@@ -1262,7 +1217,6 @@ static void ANA_MIDPI_sequence(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr)
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL_ARPI2)   , P_Fld(  1         , SHU_CA_DLL_ARPI2_RG_ARPI_MPDIV_CG_CA   ) \
                                                                      | P_Fld(  1         , SHU_CA_DLL_ARPI2_RG_ARPI_CG_FB_CA      ));
 
-    //CG
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DLL_ARPI2), P_Fld(0x1, SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCK_B0)
                 | P_Fld(0x1, SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B0)
                 | P_Fld(0x1, SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCTL_B0)
@@ -1291,12 +1245,11 @@ static void ANA_MIDPI_sequence(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr)
                 | P_Fld(0x1, SHU_CA_DLL_ARPI2_RG_ARPI_CG_CLKIEN)
                 | P_Fld(0x1, SHU_CA_DLL_ARPI2_RG_ARPI_MPDIV_CG_CA));
 
-    //step2:PLLGP_CK_SEL -- Initial no need it
-    //step3: PLLCK_EN disable
-    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_PLL2)           , P_Fld(  0         , SHU_PLL2_RG_RPHYPLL_ADA_MCK8X_EN_SHU     ));  //refer to MISC_DVFSCTRL2
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_PLL2)           , P_Fld(  0         , SHU_PLL2_RG_RPHYPLL_ADA_MCK8X_EN_SHU     ));
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_PHYPLL2)            , P_Fld(  0         , PHYPLL2_RG_RPHYPLL_AD_MCK8X_EN           ) \
                                                                      | P_Fld(  0         , PHYPLL2_RG_RPHYPLL_ADA_MCK8X_EN          ));
-    //step4:MIDPI_EN
+
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ1)             , P_Fld((!((tr->DQ_SEMI_OPEN)||(tr->DQ_CA_OPEN)))&&(!(tr->DQ_CKDIV4_EN)), SHU_B0_DQ1_RG_ARPI_MIDPI_EN_B0         ) \
                                                                          | P_Fld((!(tr->DQ_SEMI_OPEN))&&(tr->DQ_CKDIV4_EN), SHU_B0_DQ1_RG_ARPI_MIDPI_CKDIV4_EN_B0     ) \
                                                                          | P_Fld(   tr->PH8_DLY     , SHU_B0_DQ1_RG_ARPI_MIDPI_8PH_DLY_B0    ));
@@ -1314,7 +1267,7 @@ static void ANA_MIDPI_sequence(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr)
 
 
     }
-    else// for DSC semi-open CHA B1 and CHB B1 is different
+    else
     {
         DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
         vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ1)             , P_Fld((!tr->DQ_CA_OPEN)&&(!(tr->CA_CKDIV4_EN)), SHU_B1_DQ1_RG_ARPI_MIDPI_EN_B1         ) \
@@ -1353,7 +1306,7 @@ static void ANA_MIDPI_sequence(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr)
         DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
     }
 
-    // for both EMCP and DSC semi-open CHA CA and CHB CA settings are needed
+
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD1)        , P_Fld( (!(tr->DQ_CA_OPEN))&&(!(tr->CA_CKDIV4_EN)), SHU_CA_CMD1_RG_ARPI_MIDPI_EN_CA        ) \
                                                                      | P_Fld(   tr->CA_CKDIV4_EN , SHU_CA_CMD1_RG_ARPI_MIDPI_CKDIV4_EN_CA )
                                                                      | P_Fld(   tr->PH8_DLY     , SHU_CA_CMD1_RG_ARPI_MIDPI_8PH_DLY_CA    ));
@@ -1361,7 +1314,7 @@ static void ANA_MIDPI_sequence(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr)
 
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_SHU_MIDPI_CTRL)  , P_Fld( (!(tr->DQ_CA_OPEN))&&(!(tr->CA_CKDIV4_EN)), CA_SHU_MIDPI_CTRL_MIDPI_ENABLE_CA      ) \
                                                                      | P_Fld(   tr->CA_CKDIV4_EN , CA_SHU_MIDPI_CTRL_MIDPI_DIV4_ENABLE_CA ));
-    //step5:PI_RESETB
+
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_DLL_ARPI0)       , P_Fld(  0         , CA_DLL_ARPI0_RG_ARPI_RESETB_CA           ));
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DLL_ARPI0)       , P_Fld(  0         , B0_DLL_ARPI0_RG_ARPI_RESETB_B0           ));
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DLL_ARPI0)       , P_Fld(  0         , B1_DLL_ARPI0_RG_ARPI_RESETB_B1           ));
@@ -1369,12 +1322,11 @@ static void ANA_MIDPI_sequence(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr)
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_DLL_ARPI0)       , P_Fld(  1         , CA_DLL_ARPI0_RG_ARPI_RESETB_CA           ));
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DLL_ARPI0)       , P_Fld(  1         , B0_DLL_ARPI0_RG_ARPI_RESETB_B0           ));
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DLL_ARPI0)       , P_Fld(  1         , B1_DLL_ARPI0_RG_ARPI_RESETB_B1           ));
-    //step6: PLLCK_EN enable
-    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_PLL2)           , P_Fld(  1         , SHU_PLL2_RG_RPHYPLL_ADA_MCK8X_EN_SHU     ));  //refer to MISC_DVFSCTRL2
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_PLL2)           , P_Fld(  1         , SHU_PLL2_RG_RPHYPLL_ADA_MCK8X_EN_SHU     ));
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_PHYPLL2)            , P_Fld(  1         , PHYPLL2_RG_RPHYPLL_AD_MCK8X_EN           ) \
                                                                      | P_Fld(  1         , PHYPLL2_RG_RPHYPLL_ADA_MCK8X_EN          ));
-    //step7: release CG 8 Phase clk enable
-    //CG
+
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DLL_ARPI2), P_Fld(0x0, SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCK_B0)
                 | P_Fld(0x0, SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B0)
                 | P_Fld(0x0, SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCTL_B0)
@@ -1431,11 +1383,11 @@ static void ANA_DLL_sequence(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr,ANA_top_config_T
     ALL_SLAVE_EN = a_cfg->ALL_SLAVE_EN;
 
     mcSHOW_DBG_MSG6(("[ANA_INIT] DLL >>>>>>>> \n"));
-    //step1: DLL_RESETB
+
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD8)            , P_Fld(  1         , CA_CMD8_RG_ARDLL_RESETB_CA ));
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ8)             , P_Fld(  1         , B0_DQ8_RG_ARDLL_RESETB_B0  ));
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ8)             , P_Fld(  1         , B1_DQ8_RG_ARDLL_RESETB_B1  ));
-    //step2: master DLL_EN
+
     if(ALL_SLAVE_EN == 1)
     {
         if (tr->DQ_SEMI_OPEN)
@@ -1446,7 +1398,7 @@ static void ANA_DLL_sequence(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr,ANA_top_config_T
             mcDELAY_XNS(300);
             vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DLL1)        , P_Fld(  0                , SHU_B0_DLL1_RG_ARDLL_PHDET_EN_B0));
             vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL1)        , P_Fld(  0                , SHU_B1_DLL1_RG_ARDLL_PHDET_EN_B1));
-            mcDELAY_XNS(400); //2nd DLL > 77TMCK
+            mcDELAY_XNS(400);
         }
         else
         {
@@ -1456,7 +1408,7 @@ static void ANA_DLL_sequence(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr,ANA_top_config_T
             mcDELAY_XNS(300);
             vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DLL1)        , P_Fld(!(tr->DQ_SEMI_OPEN), SHU_B0_DLL1_RG_ARDLL_PHDET_EN_B0));
             vIO32WriteFldMulti(DRAMC_REG_ADDR(SLV_DLL_PHDET_EN_Reg.u4Addr)        , P_Fld(!(tr->DQ_SEMI_OPEN), SLV_DLL_PHDET_EN_Reg.u4Fld));
-            mcDELAY_XNS(400); //2nd DLL > 77TMCK
+            mcDELAY_XNS(400);
         }
     }
     else
@@ -1466,47 +1418,42 @@ static void ANA_DLL_sequence(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr,ANA_top_config_T
             DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
             vIO32WriteFldMulti_All(DRAMC_REG_ADDR(MS_DLL_PHDET_EN_Reg.u4Addr)        , P_Fld(  1     , MS_DLL_PHDET_EN_Reg.u4Fld));
             DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
-            mcDELAY_XNS(300); //1st DLL  > 55 TMCK
+            mcDELAY_XNS(300);
         }
         else
         {
             DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
             vIO32WriteFldMulti(DRAMC_REG_ADDR(MS_DLL_PHDET_EN_Reg.u4Addr)        , P_Fld(  1     , MS_DLL_PHDET_EN_Reg.u4Fld));
-            mcDELAY_XNS(300); //1st DLL >55T MCK
+            mcDELAY_XNS(300);
             vSetPHY2ChannelMapping(p, CHANNEL_B);
             vIO32WriteFldMulti(DRAMC_REG_ADDR(MS_DLL_PHDET_EN_Reg.u4Addr)        , P_Fld(  1     , MS_DLL_PHDET_EN_Reg.u4Fld));
             #if (CHANNEL_NUM>2)
 			    if (channel_num_auxadc > 2) {
 		            vSetPHY2ChannelMapping(p, CHANNEL_C);
         		    vIO32WriteFldMulti(DRAMC_REG_ADDR(MS_DLL_PHDET_EN_Reg.u4Addr)        , P_Fld(  1     , MS_DLL_PHDET_EN_Reg.u4Fld));
-		            mcDELAY_XNS(300); //1st DLL >55T MCK
+		            mcDELAY_XNS(300);
         		    vSetPHY2ChannelMapping(p, CHANNEL_D);
 		            vIO32WriteFldMulti(DRAMC_REG_ADDR(MS_DLL_PHDET_EN_Reg.u4Addr)        , P_Fld(  1     , MS_DLL_PHDET_EN_Reg.u4Fld));
 			    	}
             #endif
-            mcDELAY_XNS(300); //1st DLL >55T MCK
+            mcDELAY_XNS(300);
             vSetPHY2ChannelMapping(p, CHANNEL_A);
             DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
         }
         vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DLL1)        , P_Fld(!(tr->DQ_SEMI_OPEN), SHU_B0_DLL1_RG_ARDLL_PHDET_EN_B0       ));
         vIO32WriteFldMulti(DRAMC_REG_ADDR(SLV_DLL_PHDET_EN_Reg.u4Addr)        , P_Fld(!(tr->DQ_SEMI_OPEN), SLV_DLL_PHDET_EN_Reg.u4Fld       ));
-        mcDELAY_XNS(400); //2nd DLL > 77TMCK
+        mcDELAY_XNS(400);
     mcSHOW_DBG_MSG6(("[ANA_INIT] DLL <<<<<<<< \n"));
     }
 }
 
 
-//shuffle register for ANA initial flow control
-//It is not easy for initial sequence SA/DV coding --- same register for different group.  need two different method to manage it
-//1. for seqeunce
-//2. for another shuffle group need to DMA to SRAM
 void ANA_sequence_shuffle_colletion(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr)
 {
     BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0;
-    //PLL
-    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_PLL2)           , P_Fld(  1                 , SHU_PLL2_RG_RPHYPLL_ADA_MCK8X_EN_SHU   ));  //refer to MISC_DVFSCTRL2
 
-    //MIDPI
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_PLL2)           , P_Fld(  1                 , SHU_PLL2_RG_RPHYPLL_ADA_MCK8X_EN_SHU   ));
+
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DLL_ARPI2)   , P_Fld(  tr->DQ_SEMI_OPEN  , SHU_B0_DLL_ARPI2_RG_ARPI_MPDIV_CG_B0   ) \
                                                                      | P_Fld(  0                 , SHU_B0_DLL_ARPI2_RG_ARPI_CG_FB_B0      ) \
                                                                      | P_Fld(  tr->DQ_SEMI_OPEN   , SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B0));
@@ -1550,24 +1497,20 @@ void ANA_sequence_shuffle_colletion(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr)
 static void ANA_ClockOff_Sequence(DRAMC_CTX_T *p)
 {
     BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0;
-    /* Dynamic CKE to let HW disable CLK_TXD, avoiding CLK parking state violation during CKE high
-     * Note: BROADCAST is ON here
-     */
+
     CKEFixOnOff(p, TO_ALL_RANK, CKE_DYNAMIC, TO_ONE_CHANNEL);
     mcDELAY_US(1);
 
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL0), P_Fld(0, MISC_CG_CTRL0_CLK_MEM_SEL)
                                                                 | P_Fld(1, MISC_CG_CTRL0_W_CHG_MEM));
-    mcDELAY_XNS(100);//reserve 100ns period for clock mute and latch the rising edge sync condition for BCLK
+    mcDELAY_XNS(100);
     vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL0), 0, MISC_CG_CTRL0_W_CHG_MEM);
 
-    // @Darren, Fix 26M clock issue after DDR400 open loop mode (fail case: 26M/4)
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL0)      , P_Fld(  0                , MISC_CG_CTRL0_RESERVED_MISC_CG_CTRL0_BIT3_1));
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL0)      , P_Fld(  1                , MISC_CG_CTRL0_RESERVED_MISC_CG_CTRL0_BIT3_1));
     mcDELAY_XNS(100);
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL0)      , P_Fld(  0                , MISC_CG_CTRL0_RESERVED_MISC_CG_CTRL0_BIT3_1));
 
-    //DLL Off
     vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DLL1), 0, SHU_B0_DLL1_RG_ARDLL_PHDET_EN_B0);
     if (!isLP4_DSC)
     {
@@ -1584,7 +1527,6 @@ static void ANA_ClockOff_Sequence(DRAMC_CTX_T *p)
         DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
     }
 
-    //CG
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DLL_ARPI2), P_Fld(0x1, SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCK_B0)
                 | P_Fld(0x1, SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B0)
                 | P_Fld(0x1, SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCTL_B0)
@@ -1637,12 +1579,10 @@ static void ANA_ClockOff_Sequence(DRAMC_CTX_T *p)
                     | P_Fld(0x1, SHU_B1_DLL_ARPI2_RG_ARPI_MPDIV_CG_B1));
     }
 
-    //PLLCK
-    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_PLL2), 0, SHU_PLL2_RG_RPHYPLL_ADA_MCK8X_EN_SHU);  //refer to MISC_DVFSCTRL2
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_PLL2), 0, SHU_PLL2_RG_RPHYPLL_ADA_MCK8X_EN_SHU);
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_PHYPLL2), P_Fld(0, PHYPLL2_RG_RPHYPLL_AD_MCK8X_EN)
                                                         | P_Fld(0, PHYPLL2_RG_RPHYPLL_ADA_MCK8X_EN));
 
-    //PLL
     vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_PHYPLL0), 0, PHYPLL0_RG_RPHYPLL_EN);
 
     vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_PHYPLL2), 0, PHYPLL2_RG_RPHYPLL_RESETB);
@@ -1655,11 +1595,11 @@ static void TransferToSPM_Sequence(DRAMC_CTX_T *p)
     mcDELAY_XUS(20);
     vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_RG_DFS_CTRL), 0x1, MISC_RG_DFS_CTRL_SPM_DVFS_CONTROL_SEL);
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_MD32_REG_LPIF_FSM_CFG_1),
-                /* TBA set control mux in DV initial */
-                P_Fld(0x1, LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL) |                // 0: DPM, 1: SPM
-                P_Fld(0x1, LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL_2ND) |            // 0: DPM, 1: SPM
-                P_Fld(0x1, LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL_FOR_PWR) |        // 0: DPM, 1: SPM
-                P_Fld(0x1, LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL_FOR_PWR_2ND));    // 0: DPM, 1: SPM
+
+                P_Fld(0x1, LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL) |
+                P_Fld(0x1, LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL_2ND) |
+                P_Fld(0x1, LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL_FOR_PWR) |
+                P_Fld(0x1, LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL_FOR_PWR_2ND));
 }
 
 static void ANA_init_sequence(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr,ANA_top_config_T *a_cfg)
@@ -1667,7 +1607,7 @@ static void ANA_init_sequence(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr,ANA_top_config_
     mcSHOW_DBG_MSG6(("[ANA_INIT] flow start \n"));
     ANA_PLL_sequence(p);
     ANA_MIDPI_sequence(p,tr);
-    ANA_CLOCK_SWITCH(p); //clock switch supply correct FB clk. have to do this before DLL
+    ANA_CLOCK_SWITCH(p);
     ANA_DLL_sequence(p,tr,a_cfg);
     mcSHOW_DBG_MSG6(("[ANA_INIT] flow end \n"));
 }
@@ -1676,7 +1616,7 @@ void ANA_init(DRAMC_CTX_T *p)
 {
     BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0;
 #if (fcFOR_CHIP_ID == fc8195)
-    DRAM_PINMUX DRAM_Pinmux = p->DRAMPinmux; // 0: EMCP, 1: DSC, 2: MCP, 3:DSC_REV
+    DRAM_PINMUX DRAM_Pinmux = p->DRAMPinmux;
 #endif
 
     DRAMC_SUBSYS_PRE_CONFIG(p, &DV_p);
@@ -1687,7 +1627,6 @@ void ANA_init(DRAMC_CTX_T *p)
 #endif
     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CKMUX_SEL)     , P_Fld( isLP4_DSC, MISC_CKMUX_SEL_R_DMMCTLPLL_CKSEL          ));
 
-    //Disable CMD
     CmdOEOnOff(p, DISABLE, CMDOE_DIS_TO_ONE_CHANNEL);
 #if REPLACE_DFS_RG_MODE
     TransferToSPM_Sequence(p);
@@ -1695,7 +1634,7 @@ void ANA_init(DRAMC_CTX_T *p)
     ANA_ClockOff_Sequence(p);
     ANA_PHY_Config(p,A_T);
     ANA_init_sequence(p,A_D,A_T);
-    //Enable CMD
+
     CmdOEOnOff(p, ENABLE, CMDOE_DIS_TO_ONE_CHANNEL);
     LP4_single_end_DRAMC_post_config(p, M_LP4->LP4Y_EN);
     mcSHOW_DBG_MSG6(("[ANA_INIT] <<<<<<<<<<<<< \n"));