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| author | Rex-BC Chen <rex-bc.chen@mediatek.com> | 2021-07-08 15:40:06 +0800 |
|---|---|---|
| committer | Hung-Te Lin <hungte@chromium.org> | 2021-07-12 02:54:01 +0000 |
| commit | 2555bd410b104407ba137955abecf38cc89f53df (patch) | |
| tree | 227da95347338e7b5e9a3cfc5a88045570db2d0f /src/vendorcode/mediatek | |
| parent | 6db9dccc57637fa8a7ce90a7019e76f8b9e70d1d (diff) | |
| download | coreboot-2555bd410b104407ba137955abecf38cc89f53df.tar.gz coreboot-2555bd410b104407ba137955abecf38cc89f53df.tar.bz2 coreboot-2555bd410b104407ba137955abecf38cc89f53df.zip | |
vc/mediatek/mt8195: add FOR_COREBOOT define
The CONFIG(CHROMEOS) in DRAM calibration code was incorrectly used to
identify implementations for Chromebooks (in coreboot) so we want to
introduce a new flag FOR_COREBOOT to prevent confusion.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ic7a6e24f41c1fda167b5d6bb2d8a2c5c79dda8de
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56158
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/vendorcode/mediatek')
| -rw-r--r-- | src/vendorcode/mediatek/mt8195/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/vendorcode/mediatek/mt8195/dramc/dramc_top.c | 22 |
2 files changed, 13 insertions, 10 deletions
diff --git a/src/vendorcode/mediatek/mt8195/Makefile.inc b/src/vendorcode/mediatek/mt8195/Makefile.inc index 2dd5d098d642..0873ae3b2df0 100644 --- a/src/vendorcode/mediatek/mt8195/Makefile.inc +++ b/src/vendorcode/mediatek/mt8195/Makefile.inc @@ -3,3 +3,4 @@ subdirs-y += dramc CPPFLAGS_common += -Isrc/soc/mediatek/mt8195/include CPPFLAGS_common += -Isrc/soc/mediatek/common/include CPPFLAGS_common += -Isrc/vendorcode/mediatek/mt8195/dramc/include -Isrc/vendorcode/mediatek/mt8195/include +CPPFLAGS_common += -DFOR_COREBOOT diff --git a/src/vendorcode/mediatek/mt8195/dramc/dramc_top.c b/src/vendorcode/mediatek/mt8195/dramc/dramc_top.c index 1595073bb0d3..570c9763e931 100644 --- a/src/vendorcode/mediatek/mt8195/dramc/dramc_top.c +++ b/src/vendorcode/mediatek/mt8195/dramc/dramc_top.c @@ -360,7 +360,7 @@ unsigned int dramc_get_vcore_voltage(void) { #ifdef MTK_PMIC_MT6359 return mtk_regulator_get_voltage(®_vcore); -#elif CONFIG(CHROMEOS) +#elif defined(FOR_COREBOOT) return mainboard_get_regulator_vol(MTK_REGULATOR_VCORE); #else return 0; @@ -371,7 +371,7 @@ unsigned int dramc_set_vmdd_voltage(unsigned int ddr_type, unsigned int vdram) { #ifdef MTK_PMIC_MT6359 mtk_regulator_set_voltage(®_vdram, vdram, MAX_VDRAM); -#elif CONFIG(CHROMEOS) +#elif defined(FOR_COREBOOT) mainboard_set_regulator_vol(MTK_REGULATOR_VDD2, vdram); #endif return 0; @@ -381,7 +381,7 @@ unsigned int dramc_get_vmdd_voltage(unsigned int ddr_type) { #ifdef MTK_PMIC_MT6359 return mtk_regulator_get_voltage(®_vdram); -#elif CONFIG(CHROMEOS) +#elif defined(FOR_COREBOOT) return mainboard_get_regulator_vol(MTK_REGULATOR_VDD2); #else return 0; @@ -392,7 +392,7 @@ unsigned int dramc_set_vmddq_voltage(unsigned int ddr_type, unsigned int vddq) { #ifdef MTK_PMIC_MT6359 mtk_regulator_set_voltage(®_vddq, vddq, MAX_VDDQ); -#elif CONFIG(CHROMEOS) +#elif defined(FOR_COREBOOT) mainboard_set_regulator_vol(MTK_REGULATOR_VDDQ, vddq); #endif return 0; @@ -402,7 +402,7 @@ unsigned int dramc_get_vmddq_voltage(unsigned int ddr_type) { #ifdef MTK_PMIC_MT6359 return mtk_regulator_get_voltage(®_vddq); -#elif CONFIG(CHROMEOS) +#elif defined(FOR_COREBOOT) return mainboard_get_regulator_vol(MTK_REGULATOR_VDDQ); #else return 0; @@ -413,17 +413,19 @@ unsigned int dramc_set_vmddr_voltage(unsigned int vmddr) { #ifdef MTK_PMIC_MT6359 return mtk_regulator_set_voltage(®_vmddr, vmddr, MAX_VMDDR); -#elif CONFIG(CHROMEOS) +#elif defined(FOR_COREBOOT) mainboard_set_regulator_vol(MTK_REGULATOR_VMDDR, vmddr); -#endif return 0; +#else + return 0; +#endif } unsigned int dramc_get_vmddr_voltage(void) { #ifdef MTK_PMIC_MT6359 return mtk_regulator_get_voltage(®_vmddr); -#elif CONFIG(CHROMEOS) +#elif defined(FOR_COREBOOT) return mainboard_get_regulator_vol(MTK_REGULATOR_VMDDR); #else return 0; @@ -434,7 +436,7 @@ unsigned int dramc_set_vio18_voltage(unsigned int vio18) { #ifdef MTK_PMIC_MT6359 return mtk_regulator_set_voltage(®_vio18, vio18, MAX_VIO18); -#elif CONFIG(CHROMEOS) +#elif defined(FOR_COREBOOT) mainboard_set_regulator_vol(MTK_REGULATOR_VDD1, vio18); return 0; #else @@ -447,7 +449,7 @@ unsigned int dramc_get_vio18_voltage(void) { #ifdef MTK_PMIC_MT6359 return mtk_regulator_get_voltage(®_vio18); -#elif CONFIG(CHROMEOS) +#elif defined(FOR_COREBOOT) return mainboard_get_regulator_vol(MTK_REGULATOR_VDD1); #else return 0; |