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| author | Arthur Heymans <arthur@aheymans.xyz> | 2023-04-18 20:09:51 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-04-24 13:57:35 +0000 |
| commit | 7277b26f05bd357e71fc08fd33e1454bfc50b343 (patch) | |
| tree | e89139c74a958bd5bb8e2e6b42e7ba29bd834a65 /src/vendorcode/mediatek | |
| parent | 77b590eed1f1205c063e8ec2bef58fdcf91ec803 (diff) | |
| download | coreboot-7277b26f05bd357e71fc08fd33e1454bfc50b343.tar.gz coreboot-7277b26f05bd357e71fc08fd33e1454bfc50b343.tar.bz2 coreboot-7277b26f05bd357e71fc08fd33e1454bfc50b343.zip | |
vendorcode/mediatek/mt8192: Add or remove brackets
This fixes clang compilation warnings about logic problems and
superfluous brackets.
Change-Id: Ib4333b834ee2afb3147edf4c223724a851f159ba
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74545
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Xixi Chen <xixi.chen@mediatek.corp-partner.google.com>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'src/vendorcode/mediatek')
| -rw-r--r-- | src/vendorcode/mediatek/mt8192/dramc/LP4_dram_init.c | 2 | ||||
| -rw-r--r-- | src/vendorcode/mediatek/mt8192/dramc/dramc_pi_main.c | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/src/vendorcode/mediatek/mt8192/dramc/LP4_dram_init.c b/src/vendorcode/mediatek/mt8192/dramc/LP4_dram_init.c index 53fdb1687338..e98e5c2fe0ec 100644 --- a/src/vendorcode/mediatek/mt8192/dramc/LP4_dram_init.c +++ b/src/vendorcode/mediatek/mt8192/dramc/LP4_dram_init.c @@ -118,7 +118,7 @@ static void lp4_dram_init_single_rank(DRAMC_CTX_T *p,LP4_DRAM_CONFIG_T *tr,U8 ra LP4_MRS(p, 1, MR1 , rank); LP4_MRS(p, 2, MR2 , rank); //reverse the DBI - MR3 = ((!tr->DBI_WR & 1)<<7) | ((!tr->DBI_RD & 1)<<6) | (( PDDS & 7)<<3) | ((PPRP & 1)<<2) | ((tr->WR_PST & 1)<<1) | ((PU_CAL & 1)<<0); + MR3 = (((!tr->DBI_WR) & 1)<<7) | (((!tr->DBI_RD) & 1)<<6) | (( PDDS & 7)<<3) | ((PPRP & 1)<<2) | ((tr->WR_PST & 1)<<1) | ((PU_CAL & 1)<<0); LP4_MRS(p, 3, MR3 , rank); LP4_MRS(p, 11, MR11 , rank); LP4_MRS(p, 12, MR12 , rank); diff --git a/src/vendorcode/mediatek/mt8192/dramc/dramc_pi_main.c b/src/vendorcode/mediatek/mt8192/dramc/dramc_pi_main.c index c228c2cf9fca..4a98d8d3c151 100644 --- a/src/vendorcode/mediatek/mt8192/dramc/dramc_pi_main.c +++ b/src/vendorcode/mediatek/mt8192/dramc/dramc_pi_main.c @@ -987,7 +987,7 @@ static void vCalibration_Flow_LP4(DRAMC_CTX_T *p) DramcTxWindowPerbitCal(p, TX_DQ_DQS_MOVE_DQ_ONLY, FALSE, AUTOK_OFF); #if TX_K_DQM_WITH_WDBI - if ((p->DBI_W_onoff[p->dram_fsp]==DBI_ON)) + if (p->DBI_W_onoff[p->dram_fsp]==DBI_ON) { // K DQM with DBI_ON, and check DQM window spec. //msg("[TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.\n\n"); |