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| author | Kangheui Won <khwon@chromium.org> | 2021-05-14 15:17:50 +1000 |
|---|---|---|
| committer | Werner Zeh <werner.zeh@siemens.com> | 2021-06-07 05:16:20 +0000 |
| commit | 260f0f93efa809d6aab5220253ca74410d0027c2 (patch) | |
| tree | c04d7b31c9d2de76effb87066c17c41077197fed /src/vendorcode | |
| parent | 32f43e0e134eded6221dd59400b2a01860c72f76 (diff) | |
| download | coreboot-260f0f93efa809d6aab5220253ca74410d0027c2.tar.gz coreboot-260f0f93efa809d6aab5220253ca74410d0027c2.tar.bz2 coreboot-260f0f93efa809d6aab5220253ca74410d0027c2.zip | |
cezanne/psp_verstage: add reset/timer svc
The new cezanne PSP release added support for these svcs. So add those
functionality back to cezanne psp_verstage.
BUG=b:187906425
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: Id542f5ed0762f582ea966466d67ed938ecb9c1f0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55137
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/vendorcode')
| -rw-r--r-- | src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_syscall_public.h | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_syscall_public.h b/src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_syscall_public.h index 25a15e6ab078..75458c302514 100644 --- a/src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_syscall_public.h +++ b/src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_syscall_public.h @@ -37,6 +37,7 @@ #define SVC_DEBUG_PRINT 0x06 #define SVC_DEBUG_PRINT_EX 0x1A #define SVC_GET_BOOT_MODE 0x1C +#define SVC_DELAY_IN_MICRO_SECONDS 0x2F #define SVC_GET_SPI_INFO 0x60 #define SVC_MAP_SPIROM_DEVICE 0x61 #define SVC_UNMAP_SPIROM_DEVICE 0x62 @@ -44,6 +45,8 @@ #define SVC_UNMAP_FCH_IO_DEVICE 0x64 #define SVC_UPDATE_PSP_BIOS_DIR 0x65 #define SVC_COPY_DATA_FROM_UAPP 0x66 +#define SVC_RESET_SYSTEM 0x67 +#define SVC_READ_TIMER_VAL 0x68 enum psp_boot_mode { PSP_BOOT_MODE_S0 = 0x0, @@ -54,6 +57,13 @@ enum psp_boot_mode { PSP_BOOT_MODE_S5_WARM = 0x5, }; +enum reset_type +{ + RESET_TYPE_COLD = 0, + RESET_TYPE_WARM = 1, + RESET_TYPE_MAX = 2, +}; + enum fch_io_device { FCH_IO_DEVICE_SPI, FCH_IO_DEVICE_I2C, @@ -81,6 +91,12 @@ struct spirom_info { uint32_t SpiBiosSize; }; +enum psp_timer_type { + PSP_TIMER_TYPE_CHRONO = 0, + PSP_TIMER_TYPE_SECURE_RTC = 1, + PSP_TIMER_TYPE_MAX = 2, +}; + /* * Exit to the main Boot Loader. This does not return back to user application. * @@ -206,6 +222,25 @@ uint32_t svc_update_psp_bios_dir(uint32_t *psp_dir_offset, uint32_t svc_save_uapp_data(void *address, uint32_t size); /* + * Read timer raw (currently CHRONO and RTC) value + * + * Parameters: + * type - [in] Type of timer UAPP would like to read from + * (currently CHRONO and RTC) + * counter_value - [out] return the raw counter value read from + * RTC or CHRONO_LO/HI counter register + -----------------------------------------------------------------------------*/ +uint32_t svc_read_timer_val(enum psp_timer_type type, uint64_t *counter_value); + +/* + * Reset the system + * + * Parameters: + * reset_type - Cold or Warm reset + */ +uint32_t svc_reset_system(enum reset_type reset_type); + +/* * Write postcode to Port-80 * * Parameters: |