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| author | Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com> | 2021-08-06 11:00:25 +0800 |
|---|---|---|
| committer | Hung-Te Lin <hungte@chromium.org> | 2021-08-09 01:53:29 +0000 |
| commit | eb94a4a6de5d4de483c99cbaead364fdde73e2d1 (patch) | |
| tree | 0e4f51478e541b30f6e0cdd88daa061ab2580eac /src/vendorcode | |
| parent | 5889f02032bd353a6ca69ff65918128392aeead9 (diff) | |
| download | coreboot-eb94a4a6de5d4de483c99cbaead364fdde73e2d1.tar.gz coreboot-eb94a4a6de5d4de483c99cbaead364fdde73e2d1.tar.bz2 coreboot-eb94a4a6de5d4de483c99cbaead364fdde73e2d1.zip | |
vc/mediatek/mt8195: Optimize DRAM init time by limiting frequency count
Support the config MEDIATEK_DRAM_DVFS_LIMIT_FREQ_CNT to limit DRAM
frequency counts to reduce DRAM initialization time by about 100ms.
BUG=b:195274787
Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com>
Change-Id: Ibcb9a50c24f428358ef682b64946d4c91ebd81d2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'src/vendorcode')
| -rw-r--r-- | src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c b/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c index b5de592c2bbb..b5b9ae1713c2 100644 --- a/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c +++ b/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c @@ -1882,6 +1882,9 @@ int Init_DRAM(DRAM_DRAM_TYPE_T dram_type, DRAM_CBT_MODE_EXTERN_T dram_cbt_mode_e ett_fix_freq = 1; /* only 1600 & 4266 */ #endif + if (CONFIG(MEDIATEK_DRAM_DVFS_LIMIT_FREQ_CNT)) + ett_fix_freq = 0x1; // 4266, 1600 + if (ett_fix_freq != 0xff) gAndroid_DVFS_en = FALSE; |