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| author | Angel Pons <th3fanbus@gmail.com> | 2021-05-13 19:09:01 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-05-16 21:53:36 +0000 |
| commit | 01661bb6ae6a0a57b0fcc3780c8a46b50d7efb6b (patch) | |
| tree | 507a2cc622f023e12ee344f3af322a3b7242ab8a /src | |
| parent | eb90521edd48df3a0613631e131a14d50420f7b1 (diff) | |
| download | coreboot-01661bb6ae6a0a57b0fcc3780c8a46b50d7efb6b.tar.gz coreboot-01661bb6ae6a0a57b0fcc3780c8a46b50d7efb6b.tar.bz2 coreboot-01661bb6ae6a0a57b0fcc3780c8a46b50d7efb6b.zip | |
nb/intel/gm45: Guard even more macro parameters
Add brackets around the parameters to avoid operation order problems.
Tested with BUILD_TIMELESS=1, Roda RK9 remains identical.
Change-Id: Icb9d6e8bdafdac7ad820b1629d04e7bdfbcd4b3f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54280
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/northbridge/intel/gm45/raminit_read_write_training.c | 12 | ||||
| -rw-r--r-- | src/northbridge/intel/gm45/raminit_receive_enable_calibration.c | 12 |
2 files changed, 12 insertions, 12 deletions
diff --git a/src/northbridge/intel/gm45/raminit_read_write_training.c b/src/northbridge/intel/gm45/raminit_read_write_training.c index 544c523b325a..be614aebff86 100644 --- a/src/northbridge/intel/gm45/raminit_read_write_training.c +++ b/src/northbridge/intel/gm45/raminit_read_write_training.c @@ -12,13 +12,13 @@ typedef struct { } address_bunch_t; /* Read Training. */ -#define CxRDTy_MCHBAR(ch, bl) (0x14b0 + (ch * 0x0100) + ((7 - bl) * 4)) +#define CxRDTy_MCHBAR(ch, bl) (0x14b0 + ((ch) * 0x0100) + ((7 - (bl)) * 4)) #define CxRDTy_T_SHIFT 20 #define CxRDTy_T_MASK (0xf << CxRDTy_T_SHIFT) -#define CxRDTy_T(t) ((t << CxRDTy_T_SHIFT) & CxRDTy_T_MASK) +#define CxRDTy_T(t) (((t) << CxRDTy_T_SHIFT) & CxRDTy_T_MASK) #define CxRDTy_P_SHIFT 16 #define CxRDTy_P_MASK (0x7 << CxRDTy_P_SHIFT) -#define CxRDTy_P(p) ((p << CxRDTy_P_SHIFT) & CxRDTy_P_MASK) +#define CxRDTy_P(p) (((p) << CxRDTy_P_SHIFT) & CxRDTy_P_MASK) static const u32 read_training_schedule[] = { 0xfefefefe, 0x7f7f7f7f, 0xbebebebe, 0xdfdfdfdf, 0xeeeeeeee, 0xf7f7f7f7, 0xfafafafa, 0xfdfdfdfd, @@ -276,13 +276,13 @@ void raminit_read_training(const dimminfo_t *const dimms, const int s3resume) /* Write Training. */ #define CxWRTy_T_SHIFT 28 #define CxWRTy_T_MASK (0xf << CxWRTy_T_SHIFT) -#define CxWRTy_T(t) ((t << CxWRTy_T_SHIFT) & CxWRTy_T_MASK) +#define CxWRTy_T(t) (((t) << CxWRTy_T_SHIFT) & CxWRTy_T_MASK) #define CxWRTy_P_SHIFT 24 #define CxWRTy_P_MASK (0x7 << CxWRTy_P_SHIFT) -#define CxWRTy_P(p) ((p << CxWRTy_P_SHIFT) & CxWRTy_P_MASK) +#define CxWRTy_P(p) (((p) << CxWRTy_P_SHIFT) & CxWRTy_P_MASK) #define CxWRTy_F_SHIFT 18 #define CxWRTy_F_MASK (0x3 << CxWRTy_F_SHIFT) -#define CxWRTy_F(f) ((f << CxWRTy_F_SHIFT) & CxWRTy_F_MASK) +#define CxWRTy_F(f) (((f) << CxWRTy_F_SHIFT) & CxWRTy_F_MASK) #define CxWRTy_D_SHIFT 16 #define CxWRTy_D_MASK (0x3 << CxWRTy_D_SHIFT) #define CxWRTy_BELOW_D (0x3 << CxWRTy_D_SHIFT) diff --git a/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c b/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c index 0b1c789ef957..1d207468a593 100644 --- a/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c +++ b/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c @@ -5,29 +5,29 @@ #include <console/console.h> #include "gm45.h" -#define CxRECy_MCHBAR(x, y) (0x14a0 + (x * 0x0100) + ((3 - y) * 4)) +#define CxRECy_MCHBAR(x, y) (0x14a0 + ((x) * 0x0100) + ((3 - (y)) * 4)) #define CxRECy_SHIFT_L 0 #define CxRECy_MASK_L (3 << CxRECy_SHIFT_L) #define CxRECy_SHIFT_H 16 #define CxRECy_MASK_H (3 << CxRECy_SHIFT_H) #define CxRECy_T_SHIFT 28 #define CxRECy_T_MASK (0xf << CxRECy_T_SHIFT) -#define CxRECy_T(t) ((t << CxRECy_T_SHIFT) & CxRECy_T_MASK) +#define CxRECy_T(t) (((t) << CxRECy_T_SHIFT) & CxRECy_T_MASK) #define CxRECy_P_SHIFT 24 #define CxRECy_P_MASK (0x7 << CxRECy_P_SHIFT) -#define CxRECy_P(p) ((p << CxRECy_P_SHIFT) & CxRECy_P_MASK) +#define CxRECy_P(p) (((p) << CxRECy_P_SHIFT) & CxRECy_P_MASK) #define CxRECy_PH_SHIFT 22 #define CxRECy_PH_MASK (0x3 << CxRECy_PH_SHIFT) -#define CxRECy_PH(p) ((p << CxRECy_PH_SHIFT) & CxRECy_PH_MASK) +#define CxRECy_PH(p) (((p) << CxRECy_PH_SHIFT) & CxRECy_PH_MASK) #define CxRECy_PM_SHIFT 20 #define CxRECy_PM_MASK (0x3 << CxRECy_PM_SHIFT) -#define CxRECy_PM(p) ((p << CxRECy_PM_SHIFT) & CxRECy_PM_MASK) +#define CxRECy_PM(p) (((p) << CxRECy_PM_SHIFT) & CxRECy_PM_MASK) #define CxRECy_TIMING_MASK (CxRECy_T_MASK | CxRECy_P_MASK | \ CxRECy_PH_MASK | CxRECy_PM_MASK) #define CxDRT3_C_SHIFT 7 #define CxDRT3_C_MASK (0xf << CxDRT3_C_SHIFT) -#define CxDRT3_C(c) ((c << CxDRT3_C_SHIFT) & CxDRT3_C_MASK) +#define CxDRT3_C(c) (((c) << CxDRT3_C_SHIFT) & CxDRT3_C_MASK) /* group to byte-lane mapping: (cardF X group X 2 per group) */ static const char bytelane_map[2][4][2] = { /* A,B,C */{ { 0, 1 }, { 2, 3 }, { 4, 5 }, { 6, 7 } }, |